Commit Graph

21 Commits

Author SHA1 Message Date
Mahantesh Kumbar
525ff83910 gpu: nvgpu: Cleanup PMU unit header file pmu.h
Moved PMU subunits specific defines from pmu.h to
respective subunits header file by renaming properly
as needed

JIRA NVGPU-2457

Change-Id: Id29a2d5cb028fc69049738c735c5585b6276b115
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2020-12-15 14:05:52 -06:00
rmylavarapu
418f1cbd49 nvgpu: gpu: Update TU10X APP Version
-APP_VERSION_TU10X is updated with latest ucode changes
-Version taken from P4CL: 27198307

Change-Id: Id983a848ef9cc8a469e6d81d0d259585c117924d
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194835
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2020-12-15 14:05:52 -06:00
Krishna Yarlagadda
5eb7e22cf0 Revert "nvgpu: gpu: Update TU10X APP Version"
This reverts commit d9aa771f9a001a16a49825d0c4f584e9d4f78e73.

Change-Id: Ibd944437e2184cc4af92dc40ccd166245c7fbf7e
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194112
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
2020-12-15 14:05:52 -06:00
rmylavarapu
5a9d80891d nvgpu: gpu: Update TU10X APP Version
-APP_VERSION_TU10X is updated with latest ucode changes
-Version taken from P4CL: 27198307

Change-Id: Ide0f76e256ba1c787b1e0e86dfa3b54d3f5a459c
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191652
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2020-12-15 14:05:52 -06:00
Divya Singhatwaria
dc366ea4b4 gpu: nvgpu: Fix PMU destroy sequence
A call to exit the PMU state machine/kthread must
be prioritized over any other state change.
It was possible to set the state as PMU_STATE_EXIT,
signal the kthread and overwrite the state before
the kthread has had the chance to exit its loop.
This may lead to a "lost" signal, resulting in
indefinite wait during the destroy sequence.

Faulting sequence:
1. pmu_state = PMU_STATE_EXIT in nvgpu_pmu_destroy()
2. cond_signal()
3. pmu_state = PMU_STATE_LOADING_PG_BUF
4. PMU kthread wakes up
5. PMU kthread processes PMU_STATE_LOADING_PG_BUF
6. PMU kthread sleeps
7. nvgpu_pmu_destroy() waits indefinitely

This patch adds a sticky flag to indicate PMU_STATE_EXIT,
irrespective of any subsequent changes to pmu_state.

The PMU PG init kthread may wait on a call to
NVGPU_COND_WAIT_INTERRUPTIBLE, which requires a
corresponding call to nvgpu_cond_signal_interruptible()
as the core kernel code requires this task mask to
wake-up an interruptible task.

Bug 2658750
Bug 200532122

Change-Id: I61beae80673486f83bf60c703a8af88b066a1c36
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2181926
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-08-26 03:07:33 -07:00
Seema Khowala
50cfb29f36 gpu: nvgpu: Use nvgpu_cond_signal_interruptible
Use nvgpu_cond_signal_interruptible instead of nvgpu_cond_signal
for threads waiting using NVGPU_COND_WAIT_INTERRUPTIBLE.
Refer kernel/sched/core.c .

Bug 2613870

Change-Id: I82941fb3f9cd50d248854d0e376e4a3bf5223245
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2177027
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-08-19 15:56:27 -07:00
Mahantesh Kumbar
418e33dd09 gpu: nvgpu: TU10A PMU ucode version update
-TU10A PMU ucode version update for saftey branch
 TU10A PMU AUTO profile ucode
-P4 CL 26875342

JIRA NVGPU-3722

Change-Id: Id5cc20f24fc4cb0784d89621cd3e008649df4eb6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162191
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-29 05:31:21 -07:00
Mahantesh Kumbar
6be751ed11 gpu: nvgpu: dGPU PMU init message changes
-dGPU PMU init message interface updated to support RPC style init
 PMU init message changed to RPC event & made needed changes to
 handle RPC event during init stage
-Added new RPC header PMU_RM_RPC_HEADER, header from PMU to NvGPU
 which will be part of RPC events received from PMU.
-GID info moved to super-surface for dGPU, so removed GID info
 fetch from DMEM for dGPU & kept support for iGPU only.
-PMU_UNIT_INIT value for dGPU init changed

JIRA NVGPU-3723

Change-Id: I016bd1150494007a56905db23b4769e693ecd5da
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153141
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-07-29 05:27:41 -07:00
Philip Elcan
9705c86b98 gpu: nvgpu: init: move functions from gk20a.h to own header
This moves the nvgpu.common.init function prototypes from gk20a.h to a
new unit-specific header nvgpu_init.h

JIRA NVGPU-2385

Change-Id: I48c0b0e02a8064be0eda89f26cf55189ffd55803
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133845
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2019-07-23 13:26:12 -07:00
rmylavarapu
0194d8640e gpu: nvgpu: Support sending VFE_VAR dependent masks to PMU
Right now in PMU we have disabled usage of VFE cached values
as we have seen failures in 5.1.3.0 release. This patch
will send vfe_var dependent masks to PMU which will be
used for initial invalidation of dependent VFE_VAR cached
values. As a result PMU will compute the dependent VARs and
cache them.

NVGPU-3645

Change-Id: I814ae819d77270ac45b97cf2a32726992e6f4af3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137423
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-06-20 22:58:51 -07:00
rmylavarapu
b38f261981 gpu: nvgpu: Implement Pstate Board objs
Implemented parsing and sending performance table to pmu in
form of Pstate board objs under Perf_pstate unit.

NVGPU-3472

Change-Id: If8cc6373d1a03dd8f40a93a36203fa3d7127913f
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115564
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-12 00:45:43 -07:00
Abdul Salam
84a6d4e656 gpu: nvgpu: Add support for Vmax from get_status
This patch does the following
1. Get the Vmax from get_status.
2. Compare the Vmax with voltage requested to pmu.
3. Make sure requested voltage is always less that Vmax.
4. Add maximum_voltage to expose this value via sysfs.

Bug 200454682

Change-Id: I1135f387d852a13ae435b4a665a7394ed5ed762f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129500
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-04 01:15:55 -07:00
Divya Singhatwaria
3e5fda3730 gpu: nvgpu: Fix MISRA 17.7 violations for PMU-FW unit
- Rule 17.7 states that the value returned by a
  function having non-void return type shall be used.
- Fix this violation by proper error handling.

JIRA NVGPU-3419

Change-Id: Ia66906747cc2a95ea7f1ce5da16e4251ff521e53
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121936
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2019-05-26 22:36:45 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2019-05-23 00:56:55 -07:00
Mahantesh Kumbar
0a64f6cb2d gpu: nvgpu: PMU pmu.c/h header include cleanup
Some headers are not required to include in pmu.c/h as
lot of PMU code restructure happened, so removed headers
which not required anymore.

JIRA NVGPU-1972

Change-Id: Iead7f049d167cdaaaf7c75c2a5e19ae7b068fe6b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110108
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2019-05-23 00:56:45 -07:00
Divya Singhatwaria
7a18c10dbe gpu: nvgpu: Fix MISRA 16.6 violations in PMU-FW unit
- Rule 16. states that all switch statements must
  shall have atleast two switch-clauses.
- Some "default" cases were missing the "break"
  statement so fix this violation in switch
  statements.

JIRA NVGPU-3419

Change-Id: I2072c3aacf437766693cb30a07b8f6678c76d48e
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121890
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-21 21:47:54 -07:00
Mahantesh Kumbar
25364895fd gpu: nvgpu: PMU RTOS fw init update
Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.

Allocation happens at pmu early init stage & will deinit at
remove_support stage.

JIRA NVGPU-1972

Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
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2019-05-14 04:56:34 -07:00
Sagar Kamble
1262df6d70 gpu: nvgpu: fix misra rule 5.7 violations in pmuif headers
Identifier names used were already used to represent types. Fix those.
for e.g. pwr_channel in nv_pmu_pmgr_pwr_channel_union.
pmu_init_msg identifier name changed to init_msg as that is used to
represent a type.

JIRA NVGPU-3272

Change-Id: I887b66f08df1e00803d872873f6447f563675d44
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108548
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2019-05-02 04:18:49 -07:00
Abdul Salam
bc10ef568e gpu: nvgpu: Restructure boardobjgrpmask unit
This patch does the following for boardobjgrpmask unit.
1. Remove unused functions and its pointers.
2. Append public functions with nvgpu.
3. Remove unnecessary inclusion of header files.
4. Make local functions as static.
5. Rename function names to increase readibility.
6. Remove boardobj* from static functions.

Jira NVGPU-1977

Change-Id: Ie6d3bd8f55784d29ae4ba720fb3998487ad2b942
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107167
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-29 11:04:46 -07:00
Mahantesh Kumbar
ef524ee0d1 gpu: nvgpu: PG init sequence update
-Currently PG task is created for both iGPU & dGPU as part PMU init
sequence path, but task is not required for dGPU or can be skipped
if ELPG is not supported on iGPU, made changes to create PG task only
if supported else skip it, and made some functions to private as these
are required by PG UNIT only.
-PG instance is allocated & set to default properties as needed if
support is enabled else skip it.
-Made changes in dependent files as required to reflect above changes

JIRA NVGPU-1972

Change-Id: I4efb7f1814a9ad48770acea2173e66f0a4c8a9c1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-25 16:25:50 -07:00
Mahantesh Kumbar
9108ae3c62 gpu: nvgpu: create PMU FW unit
Created PMU fw unit to hold PMU RTOS f/w specific ops, images,
flags & command arguments needed for PMU RTOS ucode support.

Moved PMU fw ops from gk20a.gpu_ops to pmu.fw.ops as these ops
are needed to support different version of PMU fw version for
different chips

JIRA NVGPU-1955

Change-Id: I51385d8c20524431f07cba3378676464663deb20
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090769
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-04-24 02:34:20 -07:00