Commit Graph

15 Commits

Author SHA1 Message Date
Debarshi Dutta
92d009e796 gpu: nvgpu: add safety build flag CONFIG_NVGPU_SW_SEMAPHORE
Added the safety build flag CONFIG_NVGPU_SW_SEMAPHORE to compile out
sw semaphore implementation in NVGPU. sw semaphore is only used for
presilicon bringup of GPU and hence is not needed for safety build.

Jira NVGPU-3172

Change-Id: I6a46ef22f1e2059437f710198f4ea49a47656fef
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2164216
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-31 23:26:19 -07:00
Debarshi Dutta
f6c96f620f gpu: nvgpu: add CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag
The following functions belong to the path of kernel_mode submit and
the flag CONFIG_NVGPU_KERNEL_MODE_SUBMIT is used to compile these out
of safety builds.

channel_gk20a_alloc_priv_cmdbuf
channel_gk20a_free_prealloc_resources
channel_gk20a_joblist_add
channel_gk20a_joblist_delete
channel_gk20a_joblist_peek
channel_gk20a_prealloc_resources
nvgpu_channel
nvgpu_channel_add_job
nvgpu_channel_alloc_job
nvgpu_channel_alloc_priv_cmdbuf
nvgpu_channel_clean_up_jobs
nvgpu_channel_free_job
nvgpu_channel_free_priv_cmd_entry
nvgpu_channel_free_priv_cmd_q
nvgpu_channel_from_worker_item
nvgpu_channel_get_gpfifo_free_count
nvgpu_channel_is_prealloc_enabled
nvgpu_channel_joblist_is_empty
nvgpu_channel_joblist_lock
nvgpu_channel_joblist_unlock
nvgpu_channel_kernelmode_deinit
nvgpu_channel_poll_wdt
nvgpu_channel_set_syncpt
nvgpu_channel_setup_kernelmode
nvgpu_channel_sync_get_ref
nvgpu_channel_sync_incr
nvgpu_channel_sync_incr_user
nvgpu_channel_sync_put_ref_and_check
nvgpu_channel_sync_wait_fence_fd
nvgpu_channel_update
nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_channel_update_priv_cmd_q_and_free_entry
nvgpu_channel_wdt_continue
nvgpu_channel_wdt_handler
nvgpu_channel_wdt_init
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_rewind
nvgpu_channel_wdt_start
nvgpu_channel_wdt_stop
nvgpu_channel_worker_deinit
nvgpu_channel_worker_from_worker
nvgpu_channel_worker_init
nvgpu_channel_worker_poll_init
nvgpu_channel_worker_poll_wakeup_post_process_item
nvgpu_channel_worker_poll_wakeup_process_item
nvgpu_submit_channel_gpfifo_kernel
nvgpu_submit_channel_gpfifo_user
gk20a_userd_gp_get
gk20a_userd_pb_get
gk20a_userd_gp_put
nvgpu_fence_alloc

The following members of struct nvgpu_channel are compiled out of
safety build.

struct gpfifo_desc gpfifo;
struct priv_cmd_queue priv_cmd_q;
struct nvgpu_channel_sync *sync;
struct nvgpu_list_node worker_item;
struct nvgpu_channel_wdt wdt;

The following files are compiled out of safety build.

common/fifo/submit.c
common/sync/channe1_sync_semaphore.c
hal/fifo/userd_gv11b.c

Jira NVGPU-3479

Change-Id: If46c936477c6698f4bec3cab93906aaacb0ceabf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-30 22:04:48 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 02:56:53 -07:00
Alex Waterman
6c2c4181ae gpu: nvgpu: Create hal.mm.mm for misc MM HALs
There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.

Much of this is fairly straightforward copy/paste and updates to the
HAL init files.

The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.

JIRA NVGPU-2042

Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-01 15:06:57 -07:00
Seema Khowala
312f91f991 gpu: nvgpu: move fence_gk20a to common/fence
Move gk20a/fence_gk20a.c to common/fence/fence.c

Renamed
gk20a_fence_from_semaphore -> nvgpu_fence_from_semaphore
gk20a_fence_from_syncpt -> nvgpu_fence_from_syncpt
gk20a_alloc_fence_pool -> nvgpu_fence_pool_alloc
gk20a_free_fence_pool -> nvgpu_fence_pool_free
gk20a_alloc_fence -> nvgpu_fence_alloc
gk20a_init_fence -> nvgpu_fence_init
gk20a_fence_put -> nvgpu_fence_put
gk20a_fence_get -> nvgpu_fence_get
gk20a_fence_wait -> nvgpu_fence_wait
gk20a_fence_is_expired -> nvgpu_fence_is_expired
gk20a_fence_install_fd -> nvgpu_fence_install_fd
gk20a_fence_ops struct -> nvgpu_fence_ops struct
gk20a_fence struct -> nvgpu_fence_type struct

JIRA NVGPU-1982

Change-Id: Ife77b2c3c386ff4368683c78ca02f00c99cddb4b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093002
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-10 17:24:52 -07:00
Debarshi Dutta
6fe9bb835b gpu: nvgpu: access channel_sync via public API
struct nvgpu_channel_sync is moved to a private header i.e.
channel_sync_priv.h present in common/sync/. All accesses to callback
functions inside the struct nvgpu_channel_sync in NVGPU driver is replaced by
the public channel_sync specific APIs.

Jira NVGPU-1093

Change-Id: I52d57b3d458993203a3ac6b160fb569effbe5a66
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929783
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-26 02:12:23 -07:00
Debarshi Dutta
6456cbec85 gpu: nvgpu: separate semaphore function definitions to separate unit
Add the following public APIs.

nvgpu_channel_sync_to_semaphore
nvgpu_channel_sync_semaphore_create

struct nvgpu_channel_sync_semaphore and semaphore specific static
implementations of the channel_sync callbacks as well as
definitions of the public APIs are moved to a
separate execution unit i.e. channel_sync_semaphore.c.

Jira NVGPU-1093

Change-Id: I32c62a75ef999e8f3047e2a593f77d32cbde5646
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929781
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-26 02:12:14 -07:00
Debarshi Dutta
715d35e137 gpu: nvgpu: separate syncpoint function definitions to separate unit
Add the following syncpt specific APIs

nvgpu_channel_sync_get_syncpt_id
nvgpu_channel_sync_get_syncpt_address
nvgpu_channel_sync_wait_syncpt
nvgpu_channel_sync_to_syncpt
nvgpu_channel_sync_syncpt_create

Definition of struct nvgpu_channel_sync_syncpt and syncpoint
specific static implementations of the channel_sync callbacks
as well as definitions of the public APIs are moved to a
separate execution unit i.e. channel_sync_syncpt.c

Jira NVGPU-1093

Change-Id: Ib0163c6b9bc6dfc2ab2a2b7a5fa5027be13316e2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929780
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-26 02:12:05 -07:00
Debarshi Dutta
0eac7ed9a2 gpu: nvgpu: add public APIs for nvgpu_channel_sync
Add public APIs for accessing callback functions of struct
nvgpu_channel_sync. The following public functions are added.

nvgpu_channel_sync_wait_fence_fd
nvgpu_channel_sync_incr
nvgpu_channel_sync_incr_user
nvgpu_channel_sync_set_min_eq_max
nvgpu_channel_sync_set_safe_state

Jira NVGPU-1093

Change-Id: I1ac149f340af77c7b71dbf7fdab78931bb59203b
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929779
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-26 02:11:56 -07:00
Amurthyreddy
88d21daedb gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.

JIRA NVGPU-1019

Change-Id: Ia2ec5f1db3c7a1884efe5ba7b8b4d9ebbd021734
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921373
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-24 17:00:11 -07:00
ddutta
80b5e2b8d6 gpu: nvgpu: remove os_fence dependency from channel_sync
Move the wait_cmd_buffer programming for channel_sync->wait_fd to
channel_sync.c.  nvgpu_os_fence->program_waits
interface is now removed. channel_sync can directly retrieve
syncpt/semaphore from the interfaces of struct nvgpu_os_fence_syncpt
and struct nvgpu_os_fence_sema and use it for the wait programming.

Also, change int to u32 for some variables such as num_fences,
max_wait_size and wait_cmd_size.

Jira NVGPU-1093

Change-Id: I19c1b10d676caff49ce57861091f7f0ea65e7676
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829719
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-16 15:34:13 -07:00
Alex Waterman
966d1a08be gpu: nvgpu: Standardize HAS_SYNCPOINTs check
Nvgpu uses many ways to check if sync points are enabled. The four
ways used to be:

  platform->has_syncpoints
  g->has_syncpoints
  nvgpu_is_enabled(g, NVPGU_HAS_SYNCPOINTS)
  gk20a_platform_has_syncpoints()

This patch standardizes all usage to now be nvgpu_has_syncpoints()
which is based on gk20a_platform_has_syncpoints() - just renamed to
be general to nvgpu.

All usage of the other forms have now been consolidated. However,
under the hood nvgpu_has_syncpoints() does check the is_enabled
flag. This flag is now set where g->has_syncpoints used to be set
based on the platform data.

The basic dependency chain is this:

  nvgpu_has_syncpoints -> NVGPU_HAS_SYNCPOINTS ->
    platform->has_syncpoints

However, note: there are several places where syncpoints can be
disabled if some other driver initialization fails (for ex. host1x).
Also note that nvgpu_has_syncpoints() also considers a disable
variable set by debugfs.

Bug 2327574

Change-Id: Ia2375a80f5f2e27285e6175568dd13e6bb25fd33
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803975
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-12 17:35:07 +05:30
Debarshi Dutta
421e64aad7 gpu: nvgpu: move header location of gk20a.h
Update header path of gk20a.h in files present in common/
to <nvgpu/gk20a.h>

Jira NVGPU-597

Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832024
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-09-25 00:20:25 -07:00
ddutta
feefb7046a gpu: nvgpu: minor fixes in channel_sync.c
This patch comes as a follow up to commit
2517d59be2 containing minor fixes
i.e. changing type of 'pos' to u32 instead of int and renaming
syncpt_get_id to channel_sync_syncpt_get_id

Jira NVGPU-1086

Change-Id: I8bd9271c20d88ff5f68ccfc48a0b533844bbcaaa
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829832
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-09-20 03:27:55 -07:00
Debarshi Dutta
2517d59be2 gpu: nvgpu: move channel_sync_gk20a.* to common directory
1) Move channel_sync_gk20a.* from gk20a/ to common/ directory as they
donot program any hardware registers. Also as an add-on rename
channel_sync_gk20a.* to channel_sync.* and update the headers
in required files.
2) Rename the struct gk20a_channel_sync to struct nvgpu_channel_sync. Also,
corresponding syncpt and semaphore versions of the struct alongwith
related methods are renamed by removing "gk20a" from their names and
adding "nvgpu".
3) Add misra-c cleanups

Jira NVGPU-1086

Change-Id: I4e0e21803ca3858dd7a5fc4d2454dba1f1bfcecd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812594
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-09-17 23:39:24 -07:00