3 Commits

Author	SHA1	Message	Date
Thomas Fleury	35e9663bd0	gpu: nvgpu: move eng_method_bufers from fifo to tsg ... Moved init/deinit eng method buffers from fifo to tsg - tsg.init_eng_method_buffers - tsg.deinit_eng_method_buffers Moved gv11b_fifo_init_ramfc_eng_method_buffer to the following tsg HAL: - tsg.bind_channel_eng_method_buffers This HAL is now called during bind_channel. Added the following ramin HAL: - ramin.set_ramfc_eng_method_buffer Jira NVGPU-2979 Change-Id: I96f6ff15d2176d4e3714fa8fe65a9126b3fff82c Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2087185 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-10 10:36:28 -07:00
Thomas Fleury	46aedec681	gpu: nvgpu: create init_subctx_pdb HAL for ramin ... Add the followin ramin HAL: - ramin.init_subctx_pdb Moved code from mm to ramin: - gv11b_ramin_init_subctx_pdb Jira NVGPU-3015 Change-Id: I6690b5c30055c65778e55f552bea822c0640e815 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2087952 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-03 09:56:29 -07:00
Thomas Fleury	26a94593e5	gpu: nvgpu: add set_gr_ptr to ramin ... Added ramin unit under common/fifo Added hal to set gr ctx (or subctx) in ramin: - ramin.set_gr_ptr Implemented - gk20a_ramin_set_gr_ptr - gv11b_ramin_set_gr_ptr Jira NVGPU-3015 Change-Id: I79d7e7c9819ecf27e02ef44a89143c567df89af8 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2075940 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-03 09:54:54 -07:00