gpu: nvgpu: create init_subctx_pdb HAL for ramin

Add the followin ramin HAL:
- ramin.init_subctx_pdb

Moved code from mm to ramin:
- gv11b_ramin_init_subctx_pdb

Jira NVGPU-3015

Change-Id: I6690b5c30055c65778e55f552bea822c0640e815
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087952
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -507,6 +507,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.set_gr_ptr = NULL,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
 		.init_pdb = gp10b_ramin_init_pdb,
+		.init_subctx_pdb = NULL,
 		.set_adr_limit = gk20a_ramin_set_adr_limit,
 	},
 	.runlist = {

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -28,6 +28,7 @@
 #include "hal/fifo/pbdma_gv11b.h"
 #include "hal/fifo/ramin_gm20b.h"
 #include "hal/fifo/ramin_gp10b.h"
+#include "hal/fifo/ramin_gv11b.h"
 #include "hal/fifo/tsg_gv11b.h"
 #include "hal/fifo/userd_gk20a.h"
 #include "hal/fifo/userd_gv11b.h"
@@ -595,6 +596,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.set_gr_ptr = NULL,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
 		.init_pdb = gp10b_ramin_init_pdb,
+		.init_subctx_pdb = gv11b_ramin_init_subctx_pdb,
 		.set_adr_limit = NULL,
 	},
 	.runlist = {

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -700,6 +700,7 @@ static const struct gpu_ops gm20b_ops = {
 		.set_gr_ptr = gk20a_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
 		.init_pdb = gk20a_ramin_init_pdb,
+		.init_subctx_pdb = NULL,
 		.set_adr_limit = gk20a_ramin_set_adr_limit,
 	},
 	.runlist = {

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -788,6 +788,7 @@ static const struct gpu_ops gp10b_ops = {
 		.set_gr_ptr = gk20a_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
 		.init_pdb = gp10b_ramin_init_pdb,
+		.init_subctx_pdb = NULL,
 		.set_adr_limit = gk20a_ramin_set_adr_limit,
 	},
 	.runlist = {

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -973,6 +973,7 @@ static const struct gpu_ops gv100_ops = {
 		.set_gr_ptr = gv11b_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
 		.init_pdb = gp10b_ramin_init_pdb,
+		.init_subctx_pdb = gv11b_ramin_init_subctx_pdb,
 		.set_adr_limit = NULL,
 	},
 	.runlist = {

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -928,6 +928,7 @@ static const struct gpu_ops gv11b_ops = {
 		.set_gr_ptr = gv11b_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
 		.init_pdb = gp10b_ramin_init_pdb,
+		.init_subctx_pdb = gv11b_ramin_init_subctx_pdb,
 		.set_adr_limit = NULL,
 	},
 	.runlist = {

drivers/gpu/nvgpu/gv11b/mm_gv11b.c

@@ -60,7 +60,9 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block,
 		g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
 	}
 
-	gv11b_init_subcontext_pdb(vm, inst_block, false);
+	if (g->ops.ramin.init_subctx_pdb != NULL) {
+		g->ops.ramin.init_subctx_pdb(g, inst_block, vm->pdb.mem, false);
+	}
 }
 
 bool gv11b_mm_mmu_fault_pending(struct gk20a *g)

drivers/gpu/nvgpu/gv11b/subctx_gv11b.c

@@ -32,17 +32,10 @@
 #include <nvgpu/gr/subctx.h>
 #include <nvgpu/gr/ctx.h>
 
-#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 
 #include "gv11b/subctx_gv11b.h"
 
-static void gv11b_subctx_commit_valid_mask(struct vm_gk20a *vm,
-				struct nvgpu_mem *inst_block);
-static void gv11b_subctx_commit_pdb(struct vm_gk20a *vm,
-				struct nvgpu_mem *inst_block,
-				bool replayable);
-
 void gv11b_free_subctx_header(struct channel_gk20a *c)
 {
 	if (c->subctx != NULL) {
@@ -50,64 +43,3 @@ void gv11b_free_subctx_header(struct channel_gk20a *c)
 	}
 }
 
-void gv11b_init_subcontext_pdb(struct vm_gk20a *vm,
-				struct nvgpu_mem *inst_block,
-				bool replayable)
-{
-	gv11b_subctx_commit_pdb(vm, inst_block, replayable);
-	gv11b_subctx_commit_valid_mask(vm, inst_block);
-
-}
-
-static void gv11b_subctx_commit_valid_mask(struct vm_gk20a *vm,
-				struct nvgpu_mem *inst_block)
-{
-	struct gk20a *g = gk20a_from_vm(vm);
-
-	/* Make all subctx pdbs valid */
-	nvgpu_mem_wr32(g, inst_block, 166, 0xffffffffU);
-	nvgpu_mem_wr32(g, inst_block, 167, 0xffffffffU);
-}
-
-static void gv11b_subctx_commit_pdb(struct vm_gk20a *vm,
-				struct nvgpu_mem *inst_block,
-				bool replayable)
-{
-	struct gk20a *g = gk20a_from_vm(vm);
-	u32 lo, hi;
-	u32 subctx_id = 0;
-	u32 format_word;
-	u32 pdb_addr_lo, pdb_addr_hi;
-	u64 pdb_addr;
-	u32 max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v();
-	u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem,
-				ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(),
-				ram_in_sc_page_dir_base_target_sys_mem_coh_v(),
-				ram_in_sc_page_dir_base_target_vid_mem_v());
-
-	pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem);
-	pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
-	pdb_addr_hi = u64_hi32(pdb_addr);
-	format_word = ram_in_sc_page_dir_base_target_f(
-		aperture, 0) |
-		ram_in_sc_page_dir_base_vol_f(
-		ram_in_sc_page_dir_base_vol_true_v(), 0) |
-		ram_in_sc_use_ver2_pt_format_f(1, 0) |
-		ram_in_sc_big_page_size_f(1, 0) |
-		ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
-
-	if (replayable) {
-		format_word |=
-			ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) |
-			ram_in_sc_page_dir_base_fault_replay_gcc_f(1, 0);
-	}
-
-	nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x",
-					format_word, pdb_addr_hi);
-	for (subctx_id = 0U; subctx_id < max_subctx_count; subctx_id++) {
-		lo = ram_in_sc_page_dir_base_vol_0_w() + (4U * subctx_id);
-		hi = ram_in_sc_page_dir_base_hi_0_w() + (4U * subctx_id);
-		nvgpu_mem_wr32(g, inst_block, lo, format_word);
-		nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi);
-	}
-}

drivers/gpu/nvgpu/gv11b/subctx_gv11b.h

@@ -2,7 +2,7 @@
  *
  * Volta GPU series Subcontext
  *
- * Copyright (c) 2016 - 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016 - 2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,8 +27,4 @@
 
 void gv11b_free_subctx_header(struct channel_gk20a *c);
 
-void gv11b_init_subcontext_pdb(struct vm_gk20a *vm,
-				struct nvgpu_mem *inst_block,
-				bool replayable);
-
 #endif /* NVGPU_SUBCTX_GV11B_H */

drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c

@@ -50,7 +50,8 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
 	if ((flags & NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE) != 0U) {
 		replayable = true;
 	}
-	gv11b_init_subcontext_pdb(ch->vm, mem, replayable);
+
+	g->ops.ramin.init_subctx_pdb(g, mem, ch->vm->pdb.mem, replayable);
 
 	nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
 		pbdma_gp_base_offset_f(

drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.c

@@ -44,3 +44,62 @@ void gv11b_ramin_set_gr_ptr(struct gk20a *g,
 	nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_ptr_hi_w(),
 		ram_in_engine_wfi_ptr_hi_f(addr_hi));
 }
+
+static void gv11b_subctx_commit_valid_mask(struct gk20a *g,
+		struct nvgpu_mem *inst_block)
+{
+	/* Make all subctx pdbs valid */
+	nvgpu_mem_wr32(g, inst_block, 166, U32_MAX);
+	nvgpu_mem_wr32(g, inst_block, 167, U32_MAX);
+}
+
+static void gv11b_subctx_commit_pdb(struct gk20a *g,
+		struct nvgpu_mem *inst_block, struct nvgpu_mem *pdb_mem,
+		bool replayable)
+{
+	u32 lo, hi;
+	u32 subctx_id = 0;
+	u32 format_word;
+	u32 pdb_addr_lo, pdb_addr_hi;
+	u64 pdb_addr;
+	u32 max_subctx_count = ram_in_sc_page_dir_base_target__size_1_v();
+	u32 aperture = nvgpu_aperture_mask(g, pdb_mem,
+				ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(),
+				ram_in_sc_page_dir_base_target_sys_mem_coh_v(),
+				ram_in_sc_page_dir_base_target_vid_mem_v());
+
+	pdb_addr = nvgpu_mem_get_addr(g, pdb_mem);
+	pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
+	pdb_addr_hi = u64_hi32(pdb_addr);
+	format_word = ram_in_sc_page_dir_base_target_f(
+		aperture, 0) |
+		ram_in_sc_page_dir_base_vol_f(
+		ram_in_sc_page_dir_base_vol_true_v(), 0) |
+		ram_in_sc_use_ver2_pt_format_f(1, 0) |
+		ram_in_sc_big_page_size_f(1, 0) |
+		ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
+
+	if (replayable) {
+		format_word |=
+			ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) |
+			ram_in_sc_page_dir_base_fault_replay_gcc_f(1, 0);
+	}
+
+	nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x",
+					format_word, pdb_addr_hi);
+	for (subctx_id = 0U; subctx_id < max_subctx_count; subctx_id++) {
+		lo = ram_in_sc_page_dir_base_vol_0_w() + (4U * subctx_id);
+		hi = ram_in_sc_page_dir_base_hi_0_w() + (4U * subctx_id);
+		nvgpu_mem_wr32(g, inst_block, lo, format_word);
+		nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi);
+	}
+}
+
+void gv11b_ramin_init_subctx_pdb(struct gk20a *g,
+		struct nvgpu_mem *inst_block, struct nvgpu_mem *pdb_mem,
+		bool replayable)
+{
+	gv11b_subctx_commit_pdb(g, inst_block, pdb_mem, replayable);
+	gv11b_subctx_commit_valid_mask(g, inst_block);
+
+}

drivers/gpu/nvgpu/hal/fifo/ramin_gv11b.h

@@ -30,5 +30,8 @@ struct nvgpu_mem;
 
 void gv11b_ramin_set_gr_ptr(struct gk20a *g,
 		struct nvgpu_mem *inst_block, u64 gpu_va);
+void gv11b_ramin_init_subctx_pdb(struct gk20a *g,
+		struct nvgpu_mem *inst_block, struct nvgpu_mem *pdb_mem,
+		bool replayable);
 
 #endif /* NVGPU_RAMIN_GV11B_H */

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1024,6 +1024,10 @@ struct gpu_ops {
 				struct nvgpu_mem *mem, u32 size);
 		void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block,
 				u64 pdb_addr, struct nvgpu_mem *pdb_mem);
+		void (*init_subctx_pdb)(struct gk20a *g,
+				struct nvgpu_mem *inst_block,
+				struct nvgpu_mem *pdb_mem,
+				bool replayable);
 		void (*set_adr_limit)(struct gk20a *g,
 				struct nvgpu_mem *inst_block, u64 va_limit);
 	} ramin;

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -1011,6 +1011,7 @@ static const struct gpu_ops tu104_ops = {
 		.set_gr_ptr = gv11b_ramin_set_gr_ptr,
 		.set_big_page_size = gm20b_ramin_set_big_page_size,
 		.init_pdb = gp10b_ramin_init_pdb,
+		.init_subctx_pdb = gv11b_ramin_init_subctx_pdb,
 		.set_adr_limit = NULL,
 	},
 	.runlist = {