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gpu: nvgpu: add set_adr_limit to ramin HAL

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Added the following HAL
- ramin.set_adr_limit

Jira NVGPU-3015

Change-Id: I7982bbf46a2f26cfba3b4f5986b533f79b299038
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077839
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-03-20 14:12:46 -07:00
committed by mobile promotions
parent ba4bfe7fdf
commit 04e156f09d
11 changed files with 22 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
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@@ -25,6 +25,7 @@
#include "hal/fifo/engines_gm20b.h"
#include "hal/fifo/pbdma_gm20b.h"
#include "hal/fifo/pbdma_gp10b.h"
#include "hal/fifo/ramin_gk20a.h"
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include "hal/fifo/userd_gk20a.h"
@@ -506,6 +507,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.set_gr_ptr = NULL,
.set_big_page_size = gm20b_ramin_set_big_page_size,
.init_pdb = gp10b_ramin_init_pdb,
.set_adr_limit = gk20a_ramin_set_adr_limit,
},
.runlist = {
.reschedule = NULL,

1
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
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@@ -595,6 +595,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.set_gr_ptr = NULL,
.set_big_page_size = gm20b_ramin_set_big_page_size,
.init_pdb = gp10b_ramin_init_pdb,
.set_adr_limit = NULL,
},
.runlist = {
.reschedule = NULL,

6
drivers/gpu/nvgpu/gk20a/mm_gk20a.c
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@@ -384,11 +384,7 @@ void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(),
u64_lo32(vm->va_limit - 1U) & ~0xfffU);
nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(),
ram_in_adr_limit_hi_f(u64_hi32(vm->va_limit - 1U)));
g->ops.ramin.set_adr_limit(g, inst_block, vm->va_limit - 1U);
if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);

1
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
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@@ -700,6 +700,7 @@ static const struct gpu_ops gm20b_ops = {
.set_gr_ptr = gk20a_ramin_set_gr_ptr,
.set_big_page_size = gm20b_ramin_set_big_page_size,
.init_pdb = gk20a_ramin_init_pdb,
.set_adr_limit = gk20a_ramin_set_adr_limit,
},
.runlist = {
.update_for_channel = gk20a_runlist_update_for_channel,

1
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -788,6 +788,7 @@ static const struct gpu_ops gp10b_ops = {
.set_gr_ptr = gk20a_ramin_set_gr_ptr,
.set_big_page_size = gm20b_ramin_set_big_page_size,
.init_pdb = gp10b_ramin_init_pdb,
.set_adr_limit = gk20a_ramin_set_adr_limit,
},
.runlist = {
.reschedule = gk20a_runlist_reschedule,

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -973,6 +973,7 @@ static const struct gpu_ops gv100_ops = {
.set_gr_ptr = gv11b_ramin_set_gr_ptr,
.set_big_page_size = gm20b_ramin_set_big_page_size,
.init_pdb = gp10b_ramin_init_pdb,
.set_adr_limit = NULL,
},
.runlist = {
.update_for_channel = gk20a_runlist_update_for_channel,

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -928,6 +928,7 @@ static const struct gpu_ops gv11b_ops = {
.set_gr_ptr = gv11b_ramin_set_gr_ptr,
.set_big_page_size = gm20b_ramin_set_big_page_size,
.init_pdb = gp10b_ramin_init_pdb,
.set_adr_limit = NULL,
},
.runlist = {
.reschedule = gv11b_runlist_reschedule,

9
drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.c
View File

@@ -63,3 +63,12 @@ void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
ram_in_page_dir_base_hi_f(pdb_addr_hi));
}
void gk20a_ramin_set_adr_limit(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 va_limit)
{
nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_lo_w(),
u64_lo32(va_limit - 1U) & ~0xfffU);
nvgpu_mem_wr32(g, inst_block, ram_in_adr_limit_hi_w(),
ram_in_adr_limit_hi_f(u64_hi32(va_limit - 1U)));
}

2
drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h
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@@ -31,5 +31,7 @@ void gk20a_ramin_set_gr_ptr(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 gpu_va);
void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
u64 pdb_addr, struct nvgpu_mem *pdb_mem);
void gk20a_ramin_set_adr_limit(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 va_limit);
#endif /* NVGPU_RAMIN_GK20A_H */

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1024,6 +1024,8 @@ struct gpu_ops {
struct nvgpu_mem *mem, u32 size);
void (*init_pdb)(struct gk20a *g, struct nvgpu_mem *inst_block,
u64 pdb_addr, struct nvgpu_mem *pdb_mem);
void (*set_adr_limit)(struct gk20a *g,
struct nvgpu_mem *inst_block, u64 va_limit);
} ramin;
struct {
int (*reschedule)(struct channel_gk20a *ch, bool preempt_next);

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -1011,6 +1011,7 @@ static const struct gpu_ops tu104_ops = {
.set_gr_ptr = gv11b_ramin_set_gr_ptr,
.set_big_page_size = gm20b_ramin_set_big_page_size,
.init_pdb = gp10b_ramin_init_pdb,
.set_adr_limit = NULL,
},
.runlist = {
.update_for_channel = gk20a_runlist_update_for_channel,