Commit Graph

17 Commits

Author SHA1 Message Date
Sagar Kamble
ec293030c1 gpu: nvgpu: move non-safe functions from fusa hal to non-fusa hal
Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.

JIRA NVGPU-3853

Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Deepak Nibade
99f775b622 gpu: nvgpu: compile out ctxsw stats dump in safety
CTXSW stats dump is only enabled on Linux and only through DEBUG FS.
Hence add CONFIG_DEBUG_FS compile time flag to remove corresponding
HALs in safety build.

Jira NVGPU-4028

Change-Id: I37088e1572c51ca35b651c56a4cb907eda5c9004
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201371
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00
Adeel Raza
252ddc4f05 gpu: nvgpu: add coverity whitelisting support
Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.

The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.

JIRA NVGPU-3820

Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2020-12-15 14:05:52 -06:00
Vinod G
fece8bb1b7 gpu_ nvgpu: fix misra errors in gr units
Fix MISRA 8.6 violation in gr config and interrupt units.
Rule 8.6 requires each identifier with external linkage to have
exactly one external definitions.

Move unused function definitions under CONFIG_NVGPU_HAL_NON_FUSA
checking.

Jira NVGPU-3854

Change-Id: I0661ea00ef9df700b0b928c8bf77e9a0fa4be29b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171386
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-09 00:49:21 -07:00
Nicolas Benech
f576bd8f84 gpu: nvgpu: gm20b: split HALs for FUSA
Only some HALs are functionally safe (FUSA), so this patch splits
the GM20B-related HALs into FUSA and non-FUSA source files.

JIRA NVGPU-3690

Change-Id: I3a558b1f3cc713a98e9eab366c49f7ab8ee2e5a2
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156609
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-07-30 04:07:02 -07:00
Sagar Kamble
e3686b5c07 gpu: nvgpu: split gr ctxsw fusa/non-fusa hal
Moved debugger/cilp functions from gr ctxsw prog hal files for various
platforms to corresponding fusa files as currently they are enabled in
the safety build. Updated the arch yaml to reflect the non-fusa and
fusa units for gr ctxsw_prog.

JIRA NVGPU-3690

Change-Id: I188d3de223aa65816b5f511b776eb8278e221219
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156877
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-07-19 18:19:45 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-03 02:46:15 -07:00
Seshendra Gadagottu
e364102f9a gpu: nvgpu: add graphics flag for gfxp related code
Move GFXP related code under CONFIG_NVGPU_GRAPHICS flag.
Keep the NVGPU_PREEMPTION_MODE_GRAPHICS_WFI support.

JIRA NVGPU-3415

Change-Id: Ie690ac66df4b94eb113a5898d94a892fe0ce7b11
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135427
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-06-24 02:46:03 -07:00
Deepak Nibade
436549b9bf gpu: nvgpu: add cilp flag for CILP support
Add CONFIG_NVGPU_CILP flag for CILP support across all the units

Jira NVGPU-3506

Change-Id: I0c71d38f9db6f00599a5070a8cb9d75d5b5fc351
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132258
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-06-13 12:05:59 -07:00
Deepak Nibade
1239bf67a5 gpu: nvgpu: add debugger flag for hal.gr.ctxsw_prog unit
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
hal.gr.ctxsw_prog unit
Also add this flag for PM context allocation/free

Jira NVGPU-3506

Change-Id: Ib40569c7617b8b8aa3343fc89f3d8f30b1d21aa6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132254
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2019-06-13 12:05:14 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-11 09:46:24 -07:00
Vinod G
61fb688f1a gpu: nvgpu: Add flag checking for ZCULL code
Add NVGPU_GRAPHICS flag checking for ZCULL specific codes.
Define NVGPU_GRAPHICS flag for ZCULL support.
This flag is disabled for safety build now.

Jira NVGPU-3550

Change-Id: Ifd571a5e64e8fb2dfe02a87458a2986681900a6b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127515
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2019-05-31 04:08:11 -07:00
Nitin Kumbhar
1bf55ec715 gpu: nvgpu: rename secure ops to safe ops
Change secure_ops.h to safe_ops.h and rename unsigned
type operations from nvgpu_secure_* to nvgpu_safe_*.

NVGPU-3432

Change-Id: I395896405ee2e4269ced88f251b097c5043cdeef
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122571
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-21 04:37:57 -07:00
Deepak Nibade
646b08a032 gpu: nvgpu: add flag for fecs trace support in rest of the units
Add CONFIG_GK20A_CTXSW_TRACE flag for fecs trace support in rest of
the units like common.gr.utils and common.hal.gr.ctxsw_prog

Jira NVGPU-3414

Change-Id: I8f56bc38defd49a5fc30f79a35047afa7db2ffdf
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120277
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-05-20 15:46:30 -07:00
Nitin Kumbhar
4c2cee1429 gpu: nvgpu: fix ctxsw_prog CERT-C INT violations
Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:281:
cert_violation: Casting "ts >> 32" from "unsigned long long" to
 "unsigned int" without checking its value may result in lost
 or misinterpreted data.

Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:186:
cert_violation: Casting "enable" from "bool" to "unsigned int"
 without checking its value may result in lost or misinterpreted data.

JIRA NVGPU-3410

Change-Id: I4879c8e09d8498bb2377b166035ae0e79adf8870
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119397
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-20 04:37:18 -07:00
Scott Long
89c1ec07b1 gpu: nvgpu: MISRA 11.3 fixes to gr ctx code
MISRA rule 11.3 states that a cast shall not be performed between
a pointer to object type and a pointer to a different object type.

The following gr context routines convert a gr context buffer pointer
in the form of a u8 * to a u32 * before referencing the context buffer's
contents:

 * gm20b_ctxsw_prog_check_main_image_header_magic
 * gm20b_ctxsw_prog_check_local_header_magic
 * gm20b_ctxsw_prog_get_num_gpcs
 * gm20b_ctxsw_prog_get_num_tpcs
 * gm20b_ctxsw_prog_get_extended_buffer_size_offset
 * gm20b_ctxsw_prog_get_ppc_info
 * gm20b_ctxsw_prog_get_local_priv_register_ctl_offset

Because the gr context buffer pointer starts out as a u32 * the
conversion to a u8 * isn't strictly necessary.

So this patch eliminates the conversion and the 11.3 rule violations
accordingly.

JIRA NVGPU-782

Change-Id: I0d24b539ad6ee8e56318287ce8640764285ed54d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102986
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2019-04-26 02:04:35 -07:00
Deepak Nibade
b429101b90 gpu: nvgpu: move hal.gr.ctxsw_prog unit to hal/ directory
Move common.hal.gr.ctxsw_prog unit from common/ to hal/ directory
since whole unit provides HAL interface only

Jira NVGPU-2007

Change-Id: I855e2d4263e7e743c7917620c3a25fe534ba93fe
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083779
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-03-28 09:26:28 -07:00