Commit Graph

14 Commits

Author SHA1 Message Date
Philip Elcan
c6e784a2d9 gpu: nvgpu: priv_ring: reduce CCM for gp10b_priv_ring_isr
Reduce the code complexity of gp10b_priv_ring_isr() by making helper
functions gp10b_priv_ring_isr_handle_status0() and
gp10b_priv_ring_isr_handle_status0().

This reduces the TCC metric from 14 to 4.

JIRA NVGPU-4064

Change-Id: I87537d37b2335fe0ce7c103e2d7851b0992eaff1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2212888
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2020-12-15 14:05:52 -06:00
Philip Elcan
065f98f669 gpu: nvgpu: init: add return for all init APIs
This adds return values for all init APIs. This make all the init APIs
have the same signature. This is a prerequisite to making a table of
init functions.

JIRA NVGPU-3980

Change-Id: I5b71fd06ad248092af133ffe908e2930acb6d2b0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202973
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2020-12-15 14:05:52 -06:00
Adeel Raza
3107bc862b gpu: nvgpu: ifdef function prototypes in headers
ifdef function prototypes with CONFIG_* defines. This fixes MISRA rule
8.6 violations which complain about undefined functions.

JIRA NVGPU-3873

Change-Id: I4794eceed475672f347621ac25c09552a25d4ac1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195585
GVS: Gerrit_Virtual_Submit
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2020-12-15 14:05:52 -06:00
Adeel Raza
252ddc4f05 gpu: nvgpu: add coverity whitelisting support
Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.

The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.

JIRA NVGPU-3820

Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
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2020-12-15 14:05:52 -06:00
Nitin Kumbhar
bcc21dbd0b gpu: nvgpu: fix PRE31-C violations in priv ring and pbdma
nvgpu_err() macro with nvgpu_readl() call results in a
volatile access. This violates PRE31-C rule - "Using an unsafe
function-like macro with side effect in argument nvgpu_readl()"
due to side effect of a volatile access.

Fix this by moving nvgpu_readl() calls before nvgpu_err().

JIRA NVGPU-3908

Change-Id: I927d515c4b24cd4cfca16691918f327e06894c5a
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2178415
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-08-21 04:49:58 -07:00
Philip Elcan
a09142c231 gpu: nvgpu: priv_ring: fix CERT-C violations
CERT-C Rule INT30-C Requires that unsigned integer operations do not
wrap. Fix these violations by using the safe ops.

JIRA NVGPU-3868

Change-Id: Ifc7396146d85b34d6bd04eb16675ab6234364b1b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166258
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-08-05 16:56:23 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-07-03 02:46:15 -07:00
Sagar Kamble
5d37a9e489 gpu: nvgpu: compile out sim changes from safety build
As sim is non-safe unit compile it out. Also removed FMODEL related
nvgpu changes and unit tests from the safety build.

JIRA NVGPU-3527

Change-Id: I22c83e195a09f9150fb6f5a3afff91df2ea075b9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139455
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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2019-06-20 16:05:33 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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2019-05-30 02:18:05 -07:00
Seema Khowala
2e912e13d0 gpu: nvgpu: priv_ring MISRA fix for rule 10.3
JIRA NVGPU-3288

Change-Id: Icf0b91de37408be2c3d28c3cd442d2e4af2e13d1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110651
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2019-05-03 14:05:21 -07:00
Rajesh Devaraj
4ad98e87ad gpu: nvgpu: Enable the reporting of PRI access violation
- Enable the reporting of PRI access violation.
- While enabling PRI access violation, it has been found that PRI timeout
  reporting was added part of ptimer. Since both PRI timeout and access
  violation are logically co-related, we have decided to add them as part
  of PRIV_RING.

Jira NVGPU-3087

Change-Id: I5543f1b5d0ab01354ffff16c172a635b2df1fd26
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087824
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2019-04-04 04:08:22 -07:00
Seema Khowala
c905858565 gpu: nvgpu: add cg and pg function
Add new power/clock gating functions that can be called by
other units.

New clock_gating functions will reside in cg.c under
common/power_features/cg unit.

New power gating functions will reside in pg.c under
common/power_features/pg unit.

Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.

Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.

JIRA NVGPU-2014

Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
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2019-03-08 16:24:35 -08:00
Deepak Nibade
87b5cd6528 gpu: nvgpu: remove hw_pri_ringmaster_*.h header include from gr_gk20a.c
In gr_gk20a_init_gr_config() we right now directly access a register
from hw_pri_ringmaster_*.h h/w header to read FBP count

Add a new HAL operation to PRIV_RING unit and start using it in GR code
instead of directly accessing register
g->ops.priv_ring.get_fbp_count()

Jira NVGPU-2894

Change-Id: I8a7b5423e28ef40612f55cb2915d7a2cff2f7435
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030673
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2019-03-05 03:48:08 -08:00
Seema Khowala
0a0120c18b gpu: nvgpu: move chip specific priv_ring to hal
Move chip specific priv_ring code from common/priv_ring to
hal/priv_ring.

JIRA NVGPU-2033

Change-Id: If0354dbd444750966e799d3b8466d1bfa63e896b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2028778
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2019-02-27 13:43:47 -08:00