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gpu: nvgpu: priv_ring: fix CERT-C violations

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CERT-C Rule INT30-C Requires that unsigned integer operations do not
wrap. Fix these violations by using the safe ops.

JIRA NVGPU-3868

Change-Id: Ifc7396146d85b34d6bd04eb16675ab6234364b1b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166258
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-08-01 10:39:17 -04:00
committed by mobile promotions
parent faec0fde02
commit a09142c231
1 changed files with 14 additions and 7 deletions
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21
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c
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@@ -29,6 +29,7 @@
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/safe_ops.h>
#include <nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h>
#include <nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h>
@@ -167,19 +168,25 @@ void gp10b_priv_ring_isr(struct gk20a *g)
if ((status1 & BIT32(gpc)) == 0U) {
continue;
}
gpc_offset = gpc * gpc_stride;
gpc_offset = nvgpu_safe_mult_u32(gpc, gpc_stride);
error_info = nvgpu_readl(g,
pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc_offset);
nvgpu_safe_add_u32(
pri_ringstation_gpc_gpc0_priv_error_info_r(),
gpc_offset));
error_code = nvgpu_readl(g,
pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc_offset);
nvgpu_safe_add_u32(
pri_ringstation_gpc_gpc0_priv_error_code_r(),
gpc_offset));
nvgpu_err(g, "GPC%u write error. ADR 0x%08x "
"WRDAT 0x%08x "
"INFO 0x%08x (subid 0x%08x priv level %d), "
"CODE 0x%08x", gpc,
nvgpu_readl(g,
pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc_offset),
nvgpu_readl(g,
pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc_offset),
nvgpu_readl(g, nvgpu_safe_add_u32(
pri_ringstation_gpc_gpc0_priv_error_adr_r(),
gpc_offset)),
nvgpu_readl(g, nvgpu_safe_add_u32(
pri_ringstation_gpc_gpc0_priv_error_wrdat_r(),
gpc_offset)),
error_info,
pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info),
pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info),