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7082 Commits

Author SHA1 Message Date
dinesh
25abe6a352 gpu: nvgpu: Compile out linux nvhost 
This is added to compile out some non safety code from safety build.

JIRA NVGPU-4146

Change-Id: Ie2b05f7c1bf1d0400184ae95d39103828c28de1e
Signed-off-by: dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217415
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Philip Elcan
9169e8c048 gpu: nvgpu: mc: move mc declarations to mc.h 
Move declarations that belong to mc from gk20a.h to mc.h where they
belong.

JIRA NVGPU-2532

Change-Id: I91934ff60e2735c61d16459c04507fed6e1c96d7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214421
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
5efefe169c gpu: nvgpu: init: move is_nvgpu_gpu_state_valid out of gk20a.h 
Move the declaration of is_nvgpu_gpu_state_valid() from gk20a.h to
nvgpu_init.h and add doxygen for it.

JIRA NVGPU-2532

Change-Id: I79dcb145c9a3ea70a8d5b7cd639f799b7320e04b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214420
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 2020-12-15 14:10:29 -06:00
Philip Elcan
07e5dfc577 gpu: nvgpu: swud: doxygen for nvgpu.common.nvgpu 
Add more doxygen documentation for nvgpu.common.nvgpu unit in gk20a.h
and nvgpu_common.h.

Add ifdefs for some variables that were unnecessary in all builds.

JIRA NVGPU-2532

Change-Id: I6bcd6108f78dbdf12c4001a086d707eac45dfaaa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214419
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
6c9c51f366 gpu: nvgpu: add doxygen for static_analysis.h 
This adds doxygen documentation needed for the SWUD for the functions
and macros in static_analysis.h

JIRA NVGPU-2532

Change-Id: I85bbb3d86c211d94677343c48c18a161bfb652df
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214418
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 2020-12-15 14:10:29 -06:00
Mahantesh Kumbar
fbf219d8ba gpu: nvgpu: ACR func/struct version update for FUSA 
-Renamed ACR structs for FUSA, ACR FUSA code has struct names
 ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
 code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to  acr_blob_construct.c/h

JIRA NVGPU-2516

Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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 2020-12-15 14:10:29 -06:00
Lakshmanan M
9e1b540d87 gpu: nvgpu: add doxygen comments mm.gmmu 
Add doxygen documentation for mm.gmmu in gmmu.h.

JIRA NVGPU-4105

Change-Id: If1c33cbab26de2351a88ae74a3eb1eaecc06a0a1
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219158
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Peter Daifuku
8f42de2775 gpu: nvgpu: channel_setup_bind: must be bound to TSG 
In nvgpu_channel_setup_bind, return an error if the
channel isn't bound to a TSG, as future operations
rely on being bound.

Update usermode setup_bind test to bind channel to
the tsg before calling nvgpu_setup_bind

Manual port from rel-32

Bug 200543218

Change-Id: If33b01b8176c7488445c23080ad9d11f341bff43
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215160
(cherry picked from commit 56f8e5b878)
Reviewed-on: https://git-master.nvidia.com/r/2218885
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
8048ead0ae gpu: nvgpu: doxygen for sync HAL 
Add documentation for sync HAL that is called
from other units:
- get_sync_ro_map

Jira NVGPU-4156

Change-Id: Ie8cff8694b667304ccdcb5860de134a69e57d342
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218502
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Peter Daifuku
05c892f3f1 nvgpu: fix get_maxrate when no dvfs 
In nvgpu_linux_get_maxrate, if tegra_dvfs_get_maxrate
returns 0 (a sign that there is no dvfs support), call
nvgpu_clk_arb_get_arbiter_clk_range to get the max
gpu frequency.

Bug 200543218

Change-Id: I4f9bc0acaef98cd9dfa22f709656f4bb7e9fd349
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215161
(cherry picked from commit 12202fbdcf)
Reviewed-on: https://git-master.nvidia.com/r/2217945
GVS: Gerrit_Virtual_Submit
Reviewed-by: Luis Dib <ldib@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
76eb949edb gpu: nvgpu: add flag to disable SW quiesce 
Add NVGPU_DISABLE_SW_QUIESCE flag which can be set in unit tests
to avoid entering SW quiesce.

Jira NVGPU-4089

Change-Id: Ie44b28bf69ff86908a66bb1be8aab3d365945178
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217828
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
dabc5dd8b8 gpu: nvgpu: use init framework for sw quiesce 
Add NVGPU_INIT_TABLE_ENTRY for nvgpu_sw_quiesce_init_support.
Add g->sw_quiesce_init_done to avoid multiple initializations,
and check if deinit is needed in nvgpu_sw_quiesce_remove_support.
This avoids issues in common.init unit tests.

Jira NVGPU-4089

Change-Id: Ife3aa43d5f1f86899a895e4576e38ecc28a8e371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217779
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
5e688c35f8 gpu: nvgpu: set error notifier in SW quiesce 
For MMU and PBDMA faults, error notifier needs to be set
before entering SW quiesce. Otherwise it ends up with
default NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT.

Added nvgpu_rc_mmu_fault to:
- call g->ops.fifo.recover when recovery is enabled
- set MMU error when recovery is disabled

Updated nvgpu_rc_pbdma_fault to set PBDMA error when
recovery is disabled as well.

Wait for deferred interrupts to complete before actually
entering SW quiesce state, to make sure error notifier has
been set.

Jira NVGPU-4127

Change-Id: Ia84c723e021e397391c6c609d4bb96c06afdcc47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210909
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
10adb9accc gpu: nvgpu: unit: fix build w/ recovery disabled 
nvgpu_gr_falcon_get_fecs_mutex is compiled out when
CONFIG_NVGPU_ENGINE_RESET is undefined.

g->ops.fifo.recovery is compiled out when
CONFIG_NVGPU_RECOVERY is undefined.

Jira NVGPU-4089

Change-Id: I637517e17f5853a2b79568724177c7a411e3c1ba
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2209500
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
825381b4ae gpu: nvgpu: disable recovery for safety build 
Disable CONFIG_NVGPU_RECOVERY for safety build.

Uncorrectable errors will cause the GPU to be put gracefully into
a non-functioning state to ensure that no corrupted work is
completed because of the fault. This is because the freedom
from interference may not always be shown between the faulted and
the non-faulted TSG contexts.

Jira NVGPU-4089

Change-Id: Ice60722a3be3df980ac81c26f1370f22192bab36
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197255
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
6663a1feaf gpu: nvgpu: netlist: add doxygen for netlist.h 
Added doxygen documentation for netlist public functions and data
structures.

Moved struct ctxsw_buf_offset_map_entry to correct location from
netlist.h to gr/hwpm_map.h.

JIRA NVGPU-3929

Change-Id: Ibefd89475bcf59d01cfad83a1e702e10d70a0de1
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216186
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
3e26a25e36 gpu: nvgpu: skip doxygen for userd HAL 
All userd HALs are called from common.fifo or hal.fifo
Skip doxygen since no HAL is called from external unit.

Jira NVGPU-4157

Change-Id: Ie1d27faeb0d20b1d5f1634b1a6bb7a5e3c3c97e1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218536
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Nitin Kumbhar
2a1c899fa5 gpu: nvgpu: add doxygen for common.fuse 
Create gops header for common.fuse unit and add doxygen comments
for the public interfaces and HALs.

JIRA NVGPU-2454

Change-Id: Ic7f6e5994b3ca360185674488c24ad9a0f044fe7
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217228
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 2020-12-15 14:10:29 -06:00
Prateek sethi
72e5be2690 nvrm: nvgpu_rmos: add Doxygen documentation for soc 
- Add Doxygen documentation for soc.
- Add CONFIG_NVGPU_NON_FUSA flag for nvgpu_us_counter.

Jira NVGPU-4147

Change-Id: Ie0a9879a4bf681411f0efe16590370e12f7c3b70
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215155
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
14d64640e5 gpu: nvgpu: add doxygen comments mm.page_allocator 
Add doxygen documentation for mm.page_allocator in page_allocator.h.

Jira NVGPU-4048

Change-Id: I78ef99e3683b443eddeec30bab1bef4c74aa14bc
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206502
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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 2020-12-15 14:10:29 -06:00
ajesh
e041e25713 gpu: nvgpu: add Doxygen documentation for utils 
Add Doxygen documentation details for utils unit.

Jira NVGPU-2596

Change-Id: I78a649bdeef559c4eb1738ca2aef4cf8e33e8c1a
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201411
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
ajesh
b6574f028a gpu: nvgpu: add Doxygen documentation for rwsem 
Add Doxygen documentation details for rwsem unit.

Jira NVGPU-2596

Change-Id: I9b385531d2524f6fc58d3e6ecccedf97258aed6d
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199573
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
06fd513e1e gpu: nvgpu: move common.unit into common.mc 
nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.

JIRA NVGPU-4144

Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216106
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
417e44fb74 gpu: nvgpu: skip doxygen for ramfc HAL 
All ramfc HALs are called from common.fifo or hal.fifo
Skip doxygen since no HAL is called from external unit.

Jira NVGPU-4115

Change-Id: Ifec3ce5a9d4ac24db231759ddce1f7fa1ea90b07
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215967
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seema Khowala
a6f04e7672 gpu: nvgpu: skip doxygen for gops pbdma and pbdma_status 
pbdma gops being called outside of fifo unit are:

1) common/ce/ce_app.c 	: g->ops.pbdma.format_gpfifo_entry
   ce_app is dGPU specific.

2) os/linux/debug.c	: g->ops.pbdma.dump_status
   debug dump is non_fusa.

3) os/linux/cde.c       : g->ops.pbdma.format_gpfifo_entry
   cde is linux specific and is compiled out with
   CONFIG_NVGPU_SUPPORT_CDE.

JIRA NVGPU-4111

Change-Id: I5bdf30f9ff45a38ea683692be65455d5ca2e1d48
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215939
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Lakshmanan M
7fedc5608c gpu: nvgpu: add doxygen comments mm.kmem 
Add doxygen documentation for mm.kmem in kmem.h.

JIRA NVGPU-4041

Change-Id: I9f8140b68698c8b8f220b9aec301cbd7ae13b847
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215615
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
14b94f7099 gpu: nvgpu: doxygen for fifo HAL 
Add documentation for fifo HALs that are called
from other units.
- fifo_init_support
- fifo_suspend
- preempt_tsg
- preempt_runlists_for_rc
- intr_0_isr
- intr_1_isr

Jira NVGPU-4104

Change-Id: I7a7bc4384ef3d9cb5f0b4a6a3ecf0c9ad2de85da
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213611
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 2020-12-15 14:10:29 -06:00
Prateek sethi
f9db4a6ff5 gpu: nvgpu: add Doxygen documentation for io 
Jira NVGPU-4147

Change-Id: I3b64a88b207b4fbe7a776f36a7fbf2c8023f5168
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216943
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
ajesh
0fe7739974 gpu: nvgpu: add Doxygen documentation for bug 
Add Doxygen documentation details for bug unit.

Jira NVGPU-2596

Change-Id: I60410844431f15423b99a9fd02f068d5feb621ba
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203529
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
9dd98ce028 gpu: nvgpu: ltc: add doxygen for ltc.h 
Added doxygen documentation for ltc public functions and data structures.

JIRA NVGPU-3928

Change-Id: Ie3be86d38d756235618836fcf0e1d6b6008c04b5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214653
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Vinod G
1787e49689 gpu: nvgpu: doxygen for gr HAL 
Add doxygen support to following functions.
- gr_prepare_sw
- gr_enable_hw
- gr_init_support
- gr_suspend
In ecc subunit
- ecc_init_support
- ecc_remove_support
- detect
In setup subunit
- alloc_obj_ctx
- free_gr_ctx
- free_subctx
- set_preemption_mode
In falcon subunit
- read_fecs_ctxsw_mailbox
- dump_stats
- get_fecs_ctx_state_store_major_rev_id
- bind_instblk
- ctrl_ctxsw
In intr subunit
- nonstall_isr
- stall_isr
- flush_channel_tlb
In init subunit
- get_no_of_sm
- get_nonpes_aware_tpc
- wait_initialized
- fifo_access
- get_max_subctx_count
- detect_sm_arch
- get_supported__preemption_modes
- get_default_preemption_modes

Identified the hal ops not being called from outside
units. Placed those hals under @cond ... @endcond comments.

Each gr subunit structure definition is taken outside the
main gops_gr structure definition. This helps to give a
well structured doxygen document.

Removed unused gr.falcon hals for
submit_fecs_method_op
submit_fecs_sideband_method_op

Update doxygen comments for nvgpu_gr_enable_hw and
nvgpu_gr_intr_stall_isr functions.

Jira NVGPU-4107

Change-Id: I56a74ef07bcc21752a06e3a4f55442894bb9109f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214511
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seema Khowala
74582a1906 gpu: nvgpu: skip doxygen for tsg gops 
tsg gops being called outside of fifo unit are:

1) g->ops.tsg.post_event_id
   This is non_fusa.
2) g->ops.tsg.set_timeslice
   This is non_fusa.
3) g->ops.tsg.enable
   This is non_fusa.
4) g->ops.tsg.disable
   This is non_fusa.
5) g->ops.tsg.force_reset
   This is non_fusa.

JIRA NVGPU-4114

Change-Id: I4ba5c4a9dafb85ff6bc41e59d97d387128d1a007
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215953
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Deepak Nibade
3e935bbc94 gpu: nvgpu: remove nvgpu/nvgpu_err.h include from ecc.c 
common/ecc.c is not using any API from nvgpu/nvgpu_err.h header.
Hence remove include of nvgpu/nvgpu_err.h from common/ecc.c.

Change-Id: I13b1af80d37c063161dd12afd7341244581c8f1f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215800
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Rajesh Devaraj
e7ecc59e16 gpu: nvgpu: update description of functions in SDL 
This patch updates the description of functions in SDL error reporting.

JIRA NVGPU-4034

Change-Id: I2f81c774abe0a61fc250d4426988ce34ed8e4d37
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214259
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Prateek sethi
647e48965c gpu: nvgpu: add Doxygen documentation for intr 
Jira NVGPU-3759

Change-Id: I281fcedd06f558eb4f3612360ca5e5f8b87efea5
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214881
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Prateek sethi
5438e73cff gpu: nvgpu: SWUD for fuse unit 
- Added SWUD for the FUSA code.
- Flagged out non safe code using CONFIG_NVGPU_NON_FUSA.

Jira NVGPU-3759

Change-Id: I43dd4438c017377995a2610578f2bbf554a147ac
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213965
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
d1d400b36e gpu: nvgpu: ACR unit tests 
Add unit tests for ACR unit for the following
function:
- nvgpu_acr_prepare_ucode_blob_v1()
- nvgpu_acr_is_lsf_lazy_bootstrap()

JIRA NVGPU-3978

Change-Id: I41ea1faf5a0aaf90c14006bb2ede00f20cec1064
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206929
GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:10:24 -06:00
ajesh
95386d774f gpu: nvgpu: add Doxygen documentation for kmem. 
Add Doxygen documentation details for kmem unit.

Jira NVGPU-2596

Change-Id: I6c9fbb8d3516761f173363c72424738e65c18d13
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201455
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Thomas Fleury
1223860a4f gpu: nvgpu: doxygen for ramin HAL 
Add documentation for ramin HALs that are called
from other units.
- set_gr_ptr
- set_big_page_size
- init_pdb
- init_subctx_pdb
- init_pdb_cache_war
- deinit_pdb_cache_war
- base_shift
- alloc_size

Jira NVGPU-4116

Change-Id: Idf678174b4d162dd70054e8ee2c3c427549f1cfd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213581
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 2020-12-15 14:05:52 -06:00
Antony Clince Alex
34873d561a gpu: nvgpu: fix bug in fecs method submission 
When a method is submitted to the FECS ucode using
gm20b_gr_falcon_submit_fecs_method_op, the status of the operation
is updated in the mailbox register. The driver can choose to skip validation of
the return status by setting op.cond.ok/fail = GR_IS_UCODE_OP_SKIP. At present
the driver continues to check for mailbox status despite the flag being set and
eventually times out.

Update gm20b_gr_falcon_submit_fecs_method_op so that mailbox status check is
skipped if op.cond.ok/fail is set to GR_IS_UCODE_OP_SKIP.

Change-Id: I45514933898924debedd727dc0c83570755e5b12
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214039
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 2020-12-15 14:05:52 -06:00
Thomas Fleury
933821e048 gpu: nvgpu: doxygen for channel HAL 
Add documentation for channel HALs that are called
from other units.
- enable
- disable
- count
- suspend_all_serviceable_ch
- resume_all_serviceable_ch
- set_error_notifier

Jira NVGPU-4113

Change-Id: Ibb6069cc778bfc6e0becc55e5fb78f6e9e17e723
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213514
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 2020-12-15 14:05:52 -06:00
Thomas Fleury
c5922eba87 gpu: nvgpu: doxygen for runlist HAL 
Add documentation for runlist HAL that is called
from other units:
- reload

Jira NVGPU-4110

Change-Id: Ic5fe6293461de38b38b223b84525e43ac094d50b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214220
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 2020-12-15 14:05:52 -06:00
Thomas Fleury
cf3567f6a5 gpu: nvgpu: doxygen for engine HAL 
Add documentation for runlist HAL that is called
from other units:
- read_engine_status_info

Jira NVGPU-4112

Change-Id: I6ca10169b71d39193383d010bfb2aa7eef0a8746
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214309
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Vinod G
25f4627555 gpu: nvgpu: move gr specific gpu_ops out of gk20a.h 
move gr specific gpu_ops from gk20a.h to gops_gr.h
add gops_gr.h and struct gops_gr in gk20a.h

Change needed to doxygen gr HALs.

Jira NVGPU-4107

Change-Id: I18a55596ef9a74a02e2bca3ecc82b9cc8dfe0b8d
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213699
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:05:52 -06:00
Abhiroop Kaginalkar
461602b19a gpu: nvgpu: Print the error on PG init failure 
Print the error-code in cases where the nvgpu_pg_init
kthread could not be created.

Bug 2674712

Change-Id: I3ffe912bf5155346cb9bd87bfff7eb04fb605e6e
Signed-off-by: Abhiroop Kaginalkar <akaginalkar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180518
[akaginalkar: Rebased over pmu_pg re-arch]
(cherry picked from commit d3f732a1300e8a29574969f9d7d33e19f5125f74)
Reviewed-on: https://git-master.nvidia.com/r/2213705
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Seshendra Gadagottu
7ee17a1173 gpu: nvgpu: ltc: add ltc unit test 
Added ltc unit tests to cover all ltc APIs and code.
Also updated SWUT plan for ltc.

JIRA NVGPU-902

Change-Id: I057b92b1f2602a72fa4622c161af86c515d25218
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213653
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Peter Daifuku
77e3704d3d nvgpu: vgpu: no debugfs entries that rely on PMU 
When virtualized, the guest OS has no direct access to
PMU functionality:

- Don't create debugfs entries that rely on PMU access
- Clean up PMU vgpu HAL entries that imply that PMU access
  is supported

Bug 200543218

Change-Id: I12730b600802448a240f3de042760041d3ae7d29
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2213650
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
c188413b93 gpu: nvgpu: mm: code complexity cleanup gmmu gp10b 
This patch divides complex code segments into smaller functions to
reduce code complexity in hal gmmu gp10b_fusa code.

Jira NVGPU-4065

Change-Id: Icc453c40b4f590597df3c4ac5bcac02dcad8e1b9
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205948
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Tested-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Philip Elcan
51cf6317bb gpu: nvgpu: fb: reduce CCM for fb_int_ecc_gv11b 
Reduce code complexity for gv11b_fb_intr_handle_ecc_fillunit(),
gv11b_fb_intr_handle_ecc_hubtlb() and gv11b_fb_intr_handle_ecc_l2_tlb(),
by creating helper functions for printing errors.

This reduces the TCC metric to 9 for all 3 functions.

JIRA NVGPU-4064

Change-Id: I13169352de6f4c6bf609be16861ecfa85bad0fa6
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2212889
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Philip Elcan
c6e784a2d9 gpu: nvgpu: priv_ring: reduce CCM for gp10b_priv_ring_isr 
Reduce the code complexity of gp10b_priv_ring_isr() by making helper
functions gp10b_priv_ring_isr_handle_status0() and
gp10b_priv_ring_isr_handle_status0().

This reduces the TCC metric from 14 to 4.

JIRA NVGPU-4064

Change-Id: I87537d37b2335fe0ce7c103e2d7851b0992eaff1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2212888
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:05:52 -06:00