Add doxygen documentation for private GR structures defined in:
gr/ctx_priv.h
gr/global_ctx_priv.h
gr/obj_ctx_priv.h
gr/subctx_priv.h
Compile out struct zcull_ctx_desc with flag CONFIG_NVGPU_GRAPHICS.
Compile out struct pm_ctx_desc with flag CONFIG_NVGPU_DEBUGGER.
Compile out field golden_img_loaded with flag CONFIG_NVGPU_NON_FUSA
since it is only used for VSERVER.
Jira NVGPU-4028
Change-Id: Ic63e751ee28c6b645cc13993b16f701a9dbcf3e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201372
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Some methods are implemented in SW, and it is expected that
nvgpu driver gets illegal method interrupts for these.
Do not report illegal method error if related method could
be handled. It avoids reporting false errors to 3LSS and
more importantly avoids entering SW quiesce state.
Jira NVGPU-3896
Change-Id: I1e6ddcf20e4038398259d22957619fe7bc2e9c7d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199906
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golden image size will be set when memory allocated.
See function:
- nvgpu_gr_obj_ctx_init
If golden image size is 0, gr_golden_image should be a NULL
pointer in most cases. So add NULL pointer checking in
tpc_pg_mask_store to avoid NULL pointer exception.
Bug 2403210
Change-Id: I14df5cd94d7a4418c3089c5f84b6eab93c485ba6
Signed-off-by: Sunny Li <sunnyl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161280
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GR tick frequency needs to be set to MAX value for profiler
use cases for gp10b/gv11b/tu104 chips.
Add new HAL g->ops.ptimer.config_gr_tick_freq() that configures GR
tick frequency to MAX value and call this HAL in GPU poweron path.
This support is not needed in safety build, so compile everything
only if CONFIG_NVGPU_DEBUGGER is enabled
Bug 200289214
Change-Id: Id8378540cc67ca0041b56990f8676e3a105403a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195163
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nvgpu_cg_pg_enable|disable functions are non-safe hence compile out
power_features.c. Corresponding functions from cg.c are also not
compiled. for e.g. nvgpu_cg_elcg_enable|disable, nvgpu_cg_blcg-
_mode_enable|disable, nvgpu_cg_slcg_gr_perf_ltc_load_enable|disable,
nvgpu_cg_elcg_set_elcg|blcg|slcg_enabled.
BLCG handling in nvgpu_cg_set_mode is non-safe hence compile it out
as well.
JIRA NVGPU-2175
Change-Id: I9940cc418d84eb30979dd50a2ed4a132473312fe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168957
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Removed HS self-load & bootstrap public function as no other unit access
this function. Made changes to ACR bootstrap function to load & bootstrap
ACR HS ucode on respective Engine Falcon using Falcon unit HS ucode load
& bootstrap function.
JIRA NVGPU-3811
Change-Id: I293f12137e568610a0b95f668a8408f9fce0a5f0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195018
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Moving HS ucode bootstrap from ACR unit to Falcon unit as HS ucode
bootstrap needs to be accessed by multiple units. Currently FB unit
calls ACR unit function to do self HS load & bootstrap memory unlock
HS ucode. This adds dependency on ACR unit which is not correct. So,
moving to Falcon unit to make it generic.
JIRA NVGPU-3811
Change-Id: I3696296c9df661d821199cb93872265ef6d10bfc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195016
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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ACR HS ucode is currently loaded by pmu_bl.bin (falcon bootloader),
but ACR ucode can be loaded without bootloader support by directly
copying non-secure/secure code to respective IMEM offset along with
required data to DMEM, with this bootloader dependency is removed.
This patch uses nvgpu_acr_self_hs_load_bootstrap to directly load
acr ucode to imem using priv writes. This also removes the bootloader
related code
JIRA NVGPU-3811
Change-Id: Ie2632eb26e421de3765a99c5426471eb37bf1bc9
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2169976
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:
- misra_c_2012_directive_4_7_violation: Calling function
"nvgpu_report_*_err()" which returns error information without testing
the error information.
JIRA NVGPU-4025
Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
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Overriding of ECC feature is used only in Linux through device
tree fuse overrides. It's not supported in QNX. Hence compile
out below functions from safety build.
nvgpu_gr_get_override_ecc_val()
nvgpu_gr_override_ecc_val()
Move nvgpu_gr_get_golden_image_ptr() under CONFIG_NVGPU_DEBUGGER
Re-arrange all functions in gr_utils.c/h and move all non-safe
functions towards end of file.
Jira NVGPU-4028
Change-Id: Ie56fcf78c32a9b23d2e5f5b51701c5f8ccad62ec
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199507
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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ifdef function prototypes with CONFIG_* defines. This fixes MISRA rule
8.6 violations which complain about undefined functions.
Also moved nvgpu_channel_get_from_file prototype to ioctl_channel.h &
nvgpu_probe to driver_common.h as those are linux specific. Define
nvgpu_init_soc_vars in posix/soc.c as it is implemented in QNX.
JIRA NVGPU-3873
Change-Id: I5d2b238e1b5d1318867cd2416ac5f03cc6ab7c6a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196794
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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In some cases, we would get deadlock issue due to there are two locks
acquisition on common clk driver's lock and nvgpu driver's locks. At
the bug, inconsistent lock ordering problem will come with one thread
gets "nvgpu lock -> clk lock" and the other thread gets "clk lock ->
nvgpu lock".
Slove the latter path with one-time initializing clk_parent entry
and use cached data afterward.
Bug 2555115
Change-Id: I31c5c2728f406307e7cfd4e555f4db0c163234d8
Signed-off-by: Jeremy Ho <jeremyh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146727
(cherry picked from commit 42c2bdfb9f)
Reviewed-on: https://git-master.nvidia.com/r/2160290
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Use uintptr_t for for pointer arithmmatic instead of char *
to fix following CERT-C violations.
cert_exp36_c_violation: Pointer "char *" is more strictly aligned
than pointer "struct gk20a_event_id_data_rmos const *".
cert_exp36_c_violation: Pointer "struct nvgpu_clk_dev_rmos *" is
more strictly aligned than pointer "char *".
JIRA NVGPU-3908
JIRA NVGPU-3561
Change-Id: I9d40b3337ed0ddaf172ad4f4c9dd319996d479a1
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197151
Reviewed-by: Scott Long <scottl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add safety checks to validate precision of unsigned types.
These validations are used to justify that no security issues
exist in NvGPU driver due to CERT-C INT34-C and INT35-C
violations.
These are done early in the driver probe to ensure that
code violating CERT-C INT34-C and INT35-C rules is not run
before these checks.
JIRA NVGPU-3908
JIRA NVGPU-3561
Change-Id: Iffb8e21935d16f31c52af909689c334bc120cf7c
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195033
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Remove const from __mptr declaration to fix EXP40-C violation.
cert_exp40_c_violation: Casting pointer "__mptr" with type
"struct nvgpu_clk_dev const *" to type "char *" allows an
object defined with a const-qualified type to be modified
through use of an lvalue with non-const-qualified type
Considering implementation of container_of() a const is
not required.
JIRA NVGPU-3908
JIRA NVGPU-3561
Change-Id: Ie94c3f994a962124afcda49a178a72c9b87ba7c7
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195032
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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gr config is allocated and initialized as part of gr_init_setup_sw().
The sw setup is done before gr_init_setup_hw() where sm id table
is initialized. This makes the gr_config == NULL check redundant.
Fix the coverity issue (dereference before null check) by removing
the redundant check.
JIRA NVGPU-4026
Change-Id: I16a8700ff5fee524c2e32e75b621e74c59c8e44f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199360
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add doxygen documentation for gr/gr_falcon.h header
Also move below functions under appropriate compile time flag:
- nvgpu_gr_falcon_get_pm_ctxsw_image_size() under CONFIG_NVGPU_DEBUGGER
- nvgpu_gr_falcon_get_preempt_image_size() under CONFIG_NVGPU_GRAPHICS
- nvgpu_gr_falcon_get_fecs_mutex() under CONFIG_NVGPU_ENGINE_RESET
- nvgpu_gr_falcon_bind_fecs_elpg() under CONFIG_NVGPU_POWER_PG
Also remove CONFIG_NVGPU_GRAPHICS flag used for falcon methods related
to ELPG. Use CONFIG_NVGPU_POWER_PG instead.
Jira NVGPU-4028
Change-Id: I8b93b786a2fca90998e6c1204e0a17843bc577b0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2197148
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This patch fixes the below misra violation.
kernel/nvgpu/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b_fusa.c:209
Checker: MISRA C-2012 Rule 10.7 (Required)
kernel/nvgpu/drivers/gpu/nvgpu/hal/fifo/ctxsw_timeout_gv11b_fusa.c:209:
1. misra_c_2012_rule_10_7_violation: The width of the composite
expression "1U << 0U + active_eng_id * 1U" (8 bits) is less that the
left hand operand "ctxsw_timeout_engines" (32 bits).
Jira NVGPU-3881
Change-Id: I4b48ee224a014734d55d24d0c5865eda26d5b920
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196114
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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