Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us
Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us
Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.
Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry
Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.
Added #defines for min, max and default timeslices.
Jira NVGPU-3156
Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
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Move the gk20a_init_mm_setup_hw to common code. This function just
calls HALs to initialize various bits of HW. However, since this
code assumes that (some of) the HALs are present this code is treated
as a vGPU HAL (that is it's NULL for vGPU).
This patch also renames the MM HW init HAL.
Sicne the gv11b variant of this setup_hw HAL did have some differences
from the gk20a version the new common version required some work. The
gv11b code was copied into the common function but now the gv11b
specific calls were HAL'ified (since they will need to be anyway for
the MMU fault buf code) and protected by an if-condition.
JIRA NVGPU-2042
Change-Id: I959293394ee8793923d858ee37b7ce346096654f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104541
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Move the remaining GMMU HAL related code from the gm20b/, gp10b/,
and gv11b/ directories to new gmmu hal source files.
Also update all makefiles and HAL init code to refelct the new
location of the headers and source code.
JIRA NVGPU-2042
Change-Id: Ic9b85cc547bd0f994ad11042fc4093c517327399
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103672
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Add a threaded test for nvgpu_cmpxchg API. This test implements an
atomic increment using cmpxchg. It uses the existing arithmetic
threaded framework to use the cmpxchg_inc() function to verify 100
parallel threads increment the atomic the correct number of times.
These are L1 tests since they have longer run times and are unlikely to
regress.
JIRA NVGPU-2251
Change-Id: I9c2b68052b3a1b6ef20adfa24e7d50746902f754
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100748
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add a threaded test to verify xchg operation. Also validate the
non-atomic version will fail.
There are 100 threads spawned that each do exchanges on the same atomic
1000 times. Each thread starts with a unique value. When the test
completes, make sure the values are still unique.
These are L1 tests since they have longer run times and are unlikely to
regress.
JIRA NVGPU-2251
Change-Id: I4741df500d712e60d92e5221182be02dbeaa14ef
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081067
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.
This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.
JIRA NVGPU-2042
Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
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Rename the two native GPU GMMU map/unmap functions and update the
HAL initializations to reflect this:
gk20a_locked_gmmu_map -> nvgpu_gmmu_map_locked
gk20a_locked_gmmu_unmap -> nvgpu_gmmu_unmap_locked
This matches what other units do for handling vGPU "HAL" indirection.
Also move the function declarations to <nvgpu/gmmu.h> since these are
shared among all non-vGPU chips. But since these are still technically
HAL operations they should never be called directly. This is a bit of
an organixational issue that I have not thought through hwo to solve
yet.
Ideally they would go into a "hal/mm/gmmu/" include somewhere, but
that A) doesn't yet exist, and B) those are chip specific; these
functions are native specific. Ugh.
JIRA NVGPU-2042
Change-Id: Ibc614f2928630d12eafcec6ce73019628b44ad94
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099692
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Add threaded tests for inc_and_test, dec_and_test, and sub_and_test
operations to verify atomicity. Also, add non-atomic tests for these to
verify we are actually verifying that the operations are atomic.
The new tests initialize an atomic to a non-zero value such that the
threads executing the atomic operation will reach and pass zero. The
test verifies only 1 thread observed zero (the atomic operation
returned true). The test is executed 5000 times with 100 threads.
For example, the inc_and_test will start the atomic at -50 and 100
threads will concurrently increment the atomic. The test will verify
only one of the 100 threads observed 0.
These tests are L1 tests since we don't expect regressions in the
atomics (they are basically reusing the GCC builtins) and have longer
run times in order to make sure the non-atomic variants fail.
JIRA NVGPU-2251
Change-Id: I7811779bc7c0965b4465d420066f3cff87bfa13e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079378
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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In order to show that atomicity tests prove atomicity, we need to show
non-atomic operations fail. This patch is the first step toward that,
which is to add support for non-atomic operations.
Since the common functions for the different operations must now support
3 options (32-bit, 64-bit, and non-atomic), change the macros to
inline functions for decreased complexity and better readability.
JIRA NVGPU-2251
Change-Id: I721373af1eff02d82ade45d1668ad6781bd6d7e2
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079376
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add a new MM HAL directory to contain all MM related HAL units.
As part of this change add cache unit to the MM HAL. This contains
several related fixes:
1. Move the cache code in gk20a/mm_gk20a.c and gv11b/mm_gv11b.c to
the new cache HAL. Update makefiles and header includes to take
this into account. Also rename gk20a_{read,write}l() to their
nvgpu_ variants.
2. Update the MM gops: move the cache related functions to the new
cache HAL and update all calls to this HAL to reflect the new
name.
3. Update some direct calls to gk20a MM cache ops to pass through
the HAL instead.
4. Update the unit tests for various MM related things to use the
new MM HAL locations.
This change accomplishes two architecture design goals. Firstly it
removes a multiple HW include from mm_gk20a.c (the flush HW header).
Secondly it moves code from the gk20a/ and gv11b/ directories into
more proper locations under hal/.
JIRA NVGPU-2042
Change-Id: I91e4bdca4341be4dbb46fabd72622b917769f4a6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095749
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Moved
-mmu_fault_pending mm ops to is_mmu_fault_pending mc ops
-mmu_fault_pending fb ops to is_mmu_fault_pending fb.intr ops. This
is needed to check if mmu fault intr is pending for volta onwards.
Added
is_mmu_fault_pending fifo ops. This is needed to check if mmu fault
interrupt is pending for chips prior to volta
JIRA NVGPU-1313
Change-Id: Ie8e778387cd486cb19b18c4aee734c581dcd9229
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094895
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Moved fb interrupt handling related code to fb intr sub-unit.
Moved following hals from fb hal to fb intr hal and renamed to:
void (*enable)(struct gk20a *g);
void (*disable)(struct gk20a *g);
void (*isr)(struct gk20a *g);
gk20a_readl/writel are replaced with nvgpu_read/writel.
Hals are populated with new function names and code is modified
to call new hals.
Moved ecc interrupt to gv11b_fb_intr_handle_ecc in a separate file:
fb_intr_ecc_gv11b.c/h
JIRA NVGPU-2034
Change-Id: I80c7110c902c4e082561cf7cbe65c20eb9acb661
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090070
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A previous change that added a flag around the fault injection
mechanism broken the host userspace build. This patch fixes it
by enabling the flag and adding the appropriate source file to
the host Makefile
JIRA NVGPU-1246
Change-Id: I060a04bdd28eaf5039fe1fb0d2ad6150d0a74455
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090906
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Added the following HALs
- ramin.base_shift
- ramin.alloc_base
Use above HALs in mm, instead of using hw definitions.
Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits
Added missing #include for <nvgpu/mm.h>
Jira NVGPU-3015
Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
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Add -t/--test-level option for the unit test framework. This
correlates with the test plan levels in GVS. L0 tests are a subset of
the L1 tests. Currently, only test levels 0 and 1 are supported.
The test output has been updated to display skipped tests. Skipped
tests are not included in the test dump.
JIRA NVGPU-2251
Change-Id: Icc2ff19a81529be8526e89f70983e96040390e00
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085280
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The licenses used in the userspace folder were inconsistent.
This patch fixes the situation by ensuring all files are using the
MIT license.
JIRA NVGPU-2974
Change-Id: I8c89667f72732ff6f73e6cf4be1acd9e58a7e516
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087125
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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When run with '-v' option, the unit tests will include the execution
time for each test module in seconds. E.g.
[C] Module completed: posix_bitops (execution time: 0.607291)
Update unit.sh to run with -v option on target to get data for GVS runs
if tests start timing out.
Change-Id: I2a38ac458c5a5809777df33635e271e4dc9727de
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082015
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Unit test to target the interface.bsearch unit. The goal here is to
provide line coverage for the unit. Considering that the underlying
implementation is using POSIX's bsearch, there is no need to verify
the behavior of bsearch in depth.
JIRA NVGPU-2265
Change-Id: I93ec3193bb0f93aaa47aa0c6c44eca09320893ca
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078427
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Introduce nvgpu_bitmap_set() and nvgpu_bitmap_clear() APIs to wrap the
bitmap_set() and bitmap_clear() APIs, respectively. The new nvgpu_*
versions accept unsigned length parameters since length is logically an
unsigned value where bitmap_set and bitmap_clear accept signed values.
We inherit bitmap_set and bitmap_clear from the OS, so we can't
directly change those.
Also, change uses of the old APIs to the new ones.
These changes resolve MISRA Rule 10.3 violations for implicit assignment
of objects of different essential or narrower type.
JIRA NVGPU-2953
Change-Id: I2c8f790049232a791f248b350c485bb07452315b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077624
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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While resolving MISRA 10.8 violations in our definitions of U8_MAX,
U16_MAX, etc, some of the variants tried that looked valid created
invalid values due to integer promotions. So, for sanity, we should
validate these macros in the unit test for posix-env.
JIRA NVGPU-2955
Change-Id: I9c4b66771a875728c2bf79036e9a510bbc871bfb
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078365
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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When JAMA-related data is not being used, make sure
that the corresponding strings are still initialized
otherwise it could cause issues in QNX.
JIRA NVGPU-2937
Change-Id: I73cecf2e056820177e8973992f3b1c34f4d65d8f
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2074038
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add VM unit tests for the following requirements:
- NVGPU-RQCD-45.C1: A valid GPU virtual address is/is not generated
for the buffer passed into nvgpu_vm_map().
- NVGPU-RQCD-45.C2: When a GPU virtual address is passed into the
nvgpu_vm_map() function the resulting GPU virtual address of the
map does/does not match the requested GPU virtual address.
JIRA NVGPU-1927
Change-Id: I7c9f7204772a611ff7baa56b6434a70d5b70cd27
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2036213
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Bug fix in nvgpu_aperture_mask_raw function hits BUG() due to invalid aperture
type. This patch resolves the issue by initializing mem_wr_mem and mem_rd_mem
aperture value to APERTURE_SYSMEM type.
JIRA NVGPU-2933
Change-Id: Ib4879697781a1b8d73e9428299d489aa5228c9a0
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035197
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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