Unit tests in page_table were initializing the VM with a kernel_reserved
section that was slightly smaller than expected. Then, when the fixed
alloc to support semaphores was done, the fixed address used was actually
below the start of the kernel address space. As a result this caused an
overflow in the base shift in the buddy allocator responsible for
managing the fixed alloc.
Change-Id: I4e688d418262ac8d9d4b66b46bd32ca5456d95e8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130433
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Tested-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Move all unit test specific code in bug unit under the define
__NVGPU_UNIT_TEST__. With this change the following MISRA violations
in bug unit will be only for UT specific code,
MISRA rule 11.3
MISRA rule 21.4
MISRA rule 21.5
Jira NVGPU-3294
Change-Id: I54d3fc2bb6f1f8bc319443c522cb7036d37368e6
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129285
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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While preparing the userspace builds for safety, one flag for
fault injection went missing from the host userspace build. This
patch adds it back so that the compile flags for host are the same
as the ones defined in NV_COMPONENT_CFLAGS for target.
JIRA NVGPU-1246
Change-Id: Ia448622f7000ebd46b3b8a17520e30a4f6ccfed9
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128481
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Added coverage for
- nvgpu_tsg_open
- nvgpu_tsg_release
In order to cover branch combinatorial, a bitmask is used.
For each branch, one bit indicates if the branch is taken or not.
A loop calls the tested function with all combinations.
We could afterwards prune some combinations for branches that
directly exit the function.
Set MM_UNIFIED_MEMORY feature to avoid allocating from vidmem.
Jira NVGPU-3476
Change-Id: If2e82eabfa492b4c9ec727e175f31b53fbb4f5f1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123156
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add the ability to override an apparently non-safe profile build
with the safe profile. This let's us force the safety profile build
in the userspace build (make under userspace/) and the tmake build
used for unit testing. Doing this keeps the tmake build closer to
the userspace which helps prevent regressions in the userspace
build as it has no direct GVS coverage.
Change-Id: I00c000086aabf6a70b74cf5e052c80520653546a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123833
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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When running the unit tests on an L4T target in GVS the `-v' argument
is specified in the unit test framework. This results in many megabytes
of text logs getting dumped by the pd_cache tests. These logs consist
of seemingly endless:
02:00 5: 00:55 27: nvgpu: gpu.USS nvgpu_pd_cache_alloc_direct:165 [DBG ] PD-Alloc [D] 4096 bytes
02:00 5: 00:55 27: nvgpu: gpu.USS nvgpu_pd_cache_alloc_direct:165 [DBG ] PD-Alloc [D] 4096 bytes
02:00 5: 00:55 27: nvgpu: gpu.USS nvgpu_pd_cache_alloc_direct:165 [DBG ] PD-Alloc [D] 4096 bytes
02:00 5: 00:55 27: nvgpu: gpu.USS nvgpu_pd_cache_alloc_direct:165 [DBG ] PD-Alloc [D] 4096 bytes
This isn't very useful for debugging and generally clogs this log to
a point where finding error messages is really time consuming.
Change-Id: Idd0ee1bba7426448ed88f825344f7eddcb6b90ef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127436
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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Added pre-populated register space for gv11b:
- NV_FUSE 0x00021fff:0x00021000
Registers values were captured for Xavier on DDPX platform,
using reg_dump, after disabling railgating and ELPG.
Jira NVGPU-3476
Change-Id: Ic96f06501c3e903aef7ed635a88005332758bbb6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120663
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Added pre-populated register spaces for gv11b:
- NV_PCCSR 0x0080FFFF:0x00800000
- NV_PMC 0x00000FFF:0x00000000
- NV_PPBDMA 0x0005FFFF:0x00040000
Registers values were captured for Xavier on DDPX platform,
using reg_dump, after disabling railgating and ELPG.
Also added missing reg space unregistration for NV_TOP.
Jira NVGPU-3476
Change-Id: I8745f820819c1201846472602d7ef1872583ef4e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120657
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Since DGPU support is not available in safety build now let us skip
the gv100 fuse unit tests on that build using CONFIG_DGPU_SUPPORT.
Remove these tests from required_tests.json as well.
JIRA NVGPU-3062
Change-Id: I7ec7cd1164af8c44d798f8906aa0be89f480dca2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120275
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Since nvlink support is not required for initial safety release, disable
corresponding functionality.
nvgpu_mss_nvlink_init_credits defn. and call is now compiled out using
CONFIG_TEGRA_NVLINK config option.
JIRA NVGPU-3062
Change-Id: I402ed123f07f96125d640fb340957da4828d714a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119584
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Added pre-populated register spaces for gv11b:
- NV_PFIFO 0x00003FFF:0x00002000
- NV_PTOP 0x000227FF:0x00022400
Registers values were captured on DDPX with reg_dump,
after disabling railgating and ELPG.
This allows running nvgpu_fifo_init_support, using
gv11b HALs.
Added the following tests:
- test_fifo_init_support
- test_tsg_open
- test_tsg_release
- test_fifo_remove_support
Jira NVGPU-3476
Change-Id: Ia717d9a9d431248635d51d0c265c16c2b6806a95
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120564
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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As we plan to unit test only safety build, build libnvgpu-drv.so and the
tests in the safety config by default for host (make).
Target (tmake) userspace builds are built safe & non-safe for respective
profile qnx builds. Will update umbrella makefile later to filter all
targets out for non-safety profile builds
JIRA NVGPU-3062
Change-Id: Ic98e90f913ea08c746fde37174c473a7d81e3264
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120650
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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nvgpu userspace and test builds are prepared for both host/x86 and
target/aarch64. nvgpu common cflags file was included in the
Makefile of target builds. Include it in the host build
Makefile as well.
This makes sure we run the same config of qnx and nvgpu userspace
and test builds for MISRA, Coverage.
nvgpu shared config file defines the make variables and cflags app-
licable to nvgpu common shared by qnx, nvgpu userspace, test builds.
Note that cflags are added to variable NVGPU_COMMON_CFLAGS that need
to be used by the parent Makefile to update corresponding cflags
variable.
JIRA NVGPU-3062
Change-Id: Ia7a879698220f3b73aae3f02416cab28432531e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119319
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This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.
JIRA NVGPU-3332
Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Update the shared config file to use the safety build flag NV_BUILD_
CONFIGURATION_IS_SAFETY instead of NVGPU_REDUCED. With these changes
posix userspace and tests will be built in two configs based on this
flag.
JIRA NVGPU-3062
Change-Id: Iaf34dd1a8f66f2dd3f351365c369ed46a484a257
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Since the safety build config options for qnx build are to be adhered
by posix userspace build as well, let us create shared configs file.
Add these config options to unit tests makefile as we would need to
control the tests based on these options and tests also access the
common nvgpu functions.
JIRA NVGPU-3062
Change-Id: I292eca9ac3160eed93485afddf7c30e993e0461c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA Rule 11.2 doesn't allow conversion to or from an incomplete type
pointer, as it may result incorrect point alignment and may further lead
to undefined behavior.
MISRA Rule 16.x requires all switch statements to be well-formed with
terminating break statement for every switch-clause.
This patch fixes 11.2 and 16.x violations in common.mm.nvgpu_mem.
Jira NVGPU-3339
Change-Id: I002393cc64d44826e6954d1bf6af71bd569e862f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA rule 21.3 forbids from using calloc, malloc, realloc and free
identifiers for function or macro names. This patch renames nvgpu
allocator free operator to free_alloc to follow rule 21.3.
Jira NVGPU-3336
Change-Id: Ie9f48d567255a3e1dca70632fbe3d36b45023f3f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move the gv11b MMU fault handling code into a new mm.mmu_fault HAL.
Also move the existing gmmu_mmu_fault HAL code into this HAL as they
are basically the same logical entity.
JIRA NVGPU-2042
JIRA NVGPU-1313
Change-Id: I41d3e180c762f191d4de3237e9052bdc456f9e4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109693
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There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.
Much of this is fairly straightforward copy/paste and updates to the
HAL init files.
The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.
JIRA NVGPU-2042
Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
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The alloc_insty_block() function in the MM HAL is not a HAL. It does
not abstract any HW accesses; instead it just wraps a dma allocation.
As such remove it from the HAL and move the single gk20a implementation
to common/mm/mm.c as nvgpu_alloc_inst_block().
JIRA NVGPU-2042
Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109049
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