nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 18:16:01 +03:00
Code Issues Packages Projects Releases Wiki Activity
4,424 Commits 57 Branches 84 Tags
268c298f45cb1bc0beb0b51a3583c803010b2aff
Commit Graph

668 Commits

Author SHA1 Message Date
Terje Bergstrom
1dde902b50 Revert "gpu: nvgpu: gp10b: Force always SMMU bypass" 
This reverts commit cc9bd2dc24f562e97a87641e7436594fd3b469f2.

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: Ic4493bc7b71a2ebfb49644c91b34222dd15a9be1
Reviewed-on: http://git-master/r/830854
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:09 +05:30
Alex Waterman
528c08b501 arm64: tegra: dts: Use new SID dt-bindings 
Use bindings more specific to the ARM SMMU.

Change-Id: I0e2df8e8e7bfa51036a84e923fa06e42bbed3cd7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/812438
(cherry picked from commit 98cb259c87e9531b0a21dfd3132a3f3db07ff6f0)
Reviewed-on: http://git-master/r/831515
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
 2016-12-27 15:22:09 +05:30
Aingara Paramakuru
9ab9436268 gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheable 
Some of the allocated buffers are used during normal graphics
processing. Mark them as GPU cacheable to improve performance.

Bug 1695718

Change-Id: I71d5d1538516e966526abe5e38a557776321597f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/827087
(cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed)
Reviewed-on: http://git-master/r/828493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
f4b2a02b68 gpu: nvgpu: gp10b: Add L2 clean comptags regs 
Bug 1698618

Change-Id: I5bad939d94171d2296897260043f0e67e43802e7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829097
(cherry picked from commit a067cfeb8dda03641ba981d86bef93fa9041e18e)
Reviewed-on: http://git-master/r/829414
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
de2656300a Revert "gpu: nvgpu: gp10b: Implement sparse PDEs" 
This reverts commit c2707054192b058eec24a52c7f586b030f9ff007. It
introduces regression in T124.

Bug 1702063

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I8516c0bfe129bb1ac3d7a1983846061df8ae967b
Reviewed-on: http://git-master/r/830787
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
4ff59992af gpu: nvgpu: gp10b: set ptimer source frequency 
Set platform data with ptimer source frequency.
Removed ptimerscaling10x platform data, and use
ptimer source frequency to calculate ptimerscaling
factor.

Reviewed-on: http://git-master/r/819031
(cherry picked from commit 6849603024943184b0463233bedd95934c353663)

Change-Id: I14b0735fcb602cda2e692f6b842a5ecf469ab724
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/827301
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
fb7065a2e4 gpu: nvgpu: gp10b: Implement sparse PDEs 
Change-Id: I260958d8dea1b445f91b8d15bf76d5321bdc76d1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/758653
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
313fcdb1d3 gpu: nvgpu: gp10b: update thermal programming 
Add required fileds and values for thermal slow-down
settings in thermal header file and corrected
thermal register programming with correct values.

Bug 1695567

Reviewed-on: http://git-master/r/822200
(cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981)

Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/823013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
35e3018be1 gpu: nvgpu: gp10b: support to remove bar2 vm 
Implement function to support bar2 vm clean-up.

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/814573

Change-Id: If5d884e4e1ed87bec6284719d90e9e1963c69bed
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/815428
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Seshendra Gadagottu
242623a0a8 gpu: nvgpu: gp10b: enable clock gating features 
Enable clock gating power features: slcg, blcg and elcg

Bug 200144583

Reviewed-on: http://git-master/r/821149
(cherry picked from commit 1980d443c64e6660e3cd41b8908964c07459dcce)

Change-Id: I6ce813552fa57d0fd14dd7ed6a3d9864c88dc58b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/818636
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Sami Kiminki
428b9eb552 gpu: nvgpu: gp10b: Fix support for new color compression kinds 
Fix support for kinds C32_MS4_4CBRA and C64_MS4_4CBRA. They're both
compressible and ZBC kinds, so mark them as such, too.

Change-Id: Ide09ea79a885361ecfc3c188606799c6b2fbdd2e
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/816015
(cherry picked from commit 302b06b76aed5278286487225d6e7280b747d4b3)
Reviewed-on: http://git-master/r/816014
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:09 +05:30
Terje Bergstrom
2643f200cf gpu: nvgpu: gp10b: Use PROD value for FE_GO_IDLE_TIMEOUT 
Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value
written in gk20a_init_gr_setup_hw() instead of hard coding here.

Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/813959
 2016-12-27 15:22:08 +05:30
Deepak Nibade
35b5e65166 gpu: nvgpu: add h/w headers for pbdma_methods 
Bug 200134238

Change-Id: I263a12b7a3a74d1ab07bca03d5dda685b1e4f22f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/815128
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
9f2d5c97f9 gpu: nvgpu: gp10b: create fault buffer only once 
Create only one instance of replayable fault buffer
mapping.

Change-Id: Id766298f338ce54cfca7510cbb9e4528ef1945a3
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/814615
(cherry picked from commit 422d2ced384220668347dc8422876d75f6e8807d)
Reviewed-on: http://git-master/r/817696
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Mahantesh Kumbar
50f5c87f1c gpu: nvgpu: gp10b non-secure gpmu hw init 
call gp10b_init_pmu_setup_hw1 during non-secure boot only.

Change-Id: Ia90474c7c04edd9be029d013f1da5f73de1b5326
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/815843
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
fa467827b7 gpu: nvgpu: gp10b: Make CB size and default size same 
We used to allocate 1.5x buffer size. This leads to memory waste, as
we do not set the CB size via SW methods anymore.

Bug 1686189

Change-Id: I45cbdeadc154f59b65138f99f50a72d97511cb78
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801865
(cherry picked from commit 791f2fe03d16521206649ab90498443e91e284e2)
Reviewed-on: http://git-master/r/815683
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
f1fe07c123 gpu: nvgpu: gp10b: Fix beta CB sizing 
Handle beta CB sizing differences for GfxP versus WFI channels.

Bug 1686189

Change-Id: Icc421eeb8305f7e4156a74c957662f19504ddad7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801533
(cherry picked from commit 95b9ae4e5f3c29fdb97567d846b9d2139f1a8ec4)
Reviewed-on: http://git-master/r/815682
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
4d3f44849b gpu: nvgpu: gp10b: Report Pascal DMA copy class 
Announce supporting Pascal DMA copy class instead of Maxwell.

Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/808140
(cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7)
Reviewed-on: http://git-master/r/815679
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
959756873a gpu: nvgpu: gp10b: Fix spill buffer size 
Spill buffer size is in chunks of 256B. Multiply the size by
granularity to get the size in bytes.

Bug 1686189

Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801344
(cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0)
Reviewed-on: http://git-master/r/815680
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
a982fab351 gpu: nvgpu: gp10b: Fix pagepool max size 
If pagepool size equals max we should use zero. Add the comparison
to do that.

Bug 1686189

Change-Id: I15bd43663550b1089a726c0256b89f849c193e21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801526
(cherry picked from commit 9d89ea5ba345b19d2cff86130ba9d3c4c5f07e6e)
Reviewed-on: http://git-master/r/815681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
520b461aa7 gpu: nvgpu: gp10b: enable dma for firmware loading 
Bug 1692799

Change-Id: Idf825c954c646f649d85b8fa7f76b5b45150bfe5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/812442
(cherry picked from commit f72c0738238c3f9a034c6a8b064226f0d7d5dd63)
Reviewed-on: http://git-master/r/813978
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
8066fc9b7b gpu:nvgpu: gp10b: modify gpmu hw init 
Modify gpmu hwinit to take gp10b specific register offsets in
non-secure GPMU boot path.

Bug 1685722

Change-Id: Id6696fb20c4fd40ee1b168c952a438771721c792
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/812271
(cherry picked from commit b9408892dd08beca5f4b2e056287a2bc28ccff0e)
Reviewed-on: http://git-master/r/813979
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Deepak Nibade
8d864432f5 gpu: nvgpu: set wdt timeout for gp10b 
set platform specific channel watchdog timeout to 5s
for gp10b

Bug 200133289

Change-Id: I4478463e22a8167c2fc1235dd9a80e069a27b47c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/811509
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Matt Craighead
6f4d1bb2e7 gpu: nvgpu: gp10b: skip powergate if no BPMP 
The powergating APIs only work if the BPMP is running.  Skip
these calls if it's not available, instead of relying on
is_linsim, which doesn't work under all environments.

Change-Id: I34325847b2ebf33c5db2f31111c57d22ed28ef53
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/812415
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
1ba28cf44d gpu: nvgpu: gp10b: Force always SMMU bypass 
Bug 1688709

Change-Id: If778034225dabbd0f9e6ff843ea6f06011c432bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/807030
(cherry picked from commit 32f03899ca689f6af12760afe04cf4c8e60ebba1)
Reviewed-on: http://git-master/r/808243
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
9fb5c25782 gpu: nvgpu: gp10b: update slcg xbar prod settings 
Bug 1689806

Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/806115
(cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd)
Reviewed-on: http://git-master/r/805482
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Vijayakumar
c6766cc798 gpu :nvgpu: gp10b: add ptimer scaling factor as 1x 
bug 1603226

t18x fixes ptimer bug and ticks at 1ns.

Change-Id: I590c94957c93adf70263f81a0cdfcb8dc913639e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/799989
(cherry picked from commit 44866e195113b0a44ed2513a81dcaaf079c2a5f1)
Reviewed-on: http://git-master/r/707810
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Jussi Rasanen
040d71d07b gpu: nvgpu: fix ctag computation overflow with 8GB 
Bug 1689976

Change-Id: Ibf1c296fac4f2a2c6fcf062cbd80b3526a4fd4ed
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/806588
(cherry picked from commit 24b57989dc9636b41004bac32ee56dce90318350)
Reviewed-on: http://git-master/r/808242
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Deepak Nibade
f2b4fcdce7 gpu: nvgpu: implement set_gpc_tpc_mask for gp10b 
Bug 200137963

Change-Id: Ibd09b206620e6d6826586bb40e1125fc178dd8e4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797151
(cherry picked from commit 343c4704564f4b4f22a943a94e66d2c83f63a28f)
Reviewed-on: http://git-master/r/808241
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Deepak Nibade
d3c12a335d gpu: nvgpu: implement reset_assert/deassert for gp10b 
Implement platform specific reset_assert() and reset_deassert()
calls for gp10b

These APIs will in turn will use reset_control APIs to do
their work

Also, set force_reset_in_do_idle = true for gp10b, since
railgating is not supported yet

Bug 200137963

Change-Id: I2c0fe1273d3ecfd0c46704a44374712052ff51d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797150
(cherry picked from commit 6ac04ca84cee8a4d3b089678c81534799880712d)
Reviewed-on: http://git-master/r/808240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
d1331bd07d gpu: nvgpu: gp10b: Implement SetCoalesceBufferSize 
Implement method for setting the coalesce buffer size at runtime.

Bug 1681992

Change-Id: Ice6c00a27f642c2d68d6cd0e30c12df2e48f5374
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/802366
(cherry picked from commit bd763bc8a16b80ccc8f79b2229eccf2fe2417611)
Reviewed-on: http://git-master/r/808239
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Deepak Nibade
c9da53da4e gpu: nvgpu: fix sparse warning 
fix below sparse warning
drivers/gpu/nvgpu/gm20b/gr_gm20b.c:1055:6: warning: symbol
'gr_gm20b_enable_cde_in_fecs' was not declared. Should it be static?

Bug 200088648

Change-Id: I862100d76f2ed5669d15a8f3b8cb9211df7f98ee
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/810394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2016-12-27 15:22:08 +05:30
Leonid Moiseichuk
177a9716e2 gpu: nvgpu: enabling cyclestats for gp10b 
Enabling cyclestats and cyclestats snapshot support for gp10b (t186) devices.

Bug 1674079

Change-Id: I2e14801de3c61d180630bb9dcd2c607749814893
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/792953
Reviewed-on: http://git-master/r/806190
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
0b0ce7de09 gpu: nvgpu: gp10b: Fix steady state beta CB size 
We program the default steady state beta CB size. The default is
for deep binning, but we've disabled deep binning. As result steady
state CB size was left too high.

Bug 1683535

Change-Id: I17029078d9c83e55eec6faacfc83c6d812f8c3c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/795306
Reviewed-on: http://git-master/r/806189
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
0e6a87cf22 gpu: nvgpu: gp10b: Fix CB size for GfxP 
Program correct CB size for GfxP channels. We were accidentally
using the context image size.

Change-Id: I273215256e41e89b7d76f3294a73641804beeb79
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/792713
Reviewed-on: http://git-master/r/806188
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
1ef64423f9 gpu: nvgpu: ELPG init & statistics update 
- Required init param to start elpg
- change in statistics dump

Bug  1684939

Change-Id: Icc482c08303d0870ec2e1c18a845074968b15e77
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/802455
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/806194
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
e51dfa9d61 gpu: nvgpu: gp10b: Use clock API to enable clocks 
Use CCF to enable GPU clocks. Keep an extra reference to prevent
runtime PM callbacks from disabling clocks while GPU is powered up.

Bug 1673672

Change-Id: I8c34be5ec338fedea62aa3e05bd6bed0513bf1b6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/788814
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-on: http://git-master/r/785265
 2016-12-27 15:22:07 +05:30
Kirill Artamonov
3b08d73568 gpu: nvgpu: gp10b: add debug features for gfxp and cilp 
Add debugfs switch to force cilp and gfx preemption
Add debugfs switch to dump context switch stats on channel
destruction.

bug 1525327
bug 1581799

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66
Reviewed-on: http://git-master/r/794976
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677231
 2016-12-27 15:22:07 +05:30
Kirill Artamonov
6434195dc7 gpu: nvgpu: gp10b: update headers 
Add counters for GFXP, WFI, CTA and CILP context switches

bug 1525327
bug 1581799

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: Ifd6ee08af8a83ed827a8996725139416d81ca10e
Reviewed-on: http://git-master/r/794977
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/778761
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
3e3d83aff1 gpu: nvgpu: enable gp10b rail calls to bpmp 
Bug 200086985

Change-Id: I9eaa135b96629636a6b949ae1e3874dd3abd5138
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/794723
Reviewed-on: http://git-master/r/743217
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
8e1c566896 gpu: nvgpu: gp10b: Always disable security in sim 
Change-Id: I1fc8c4c4c71ebf84fe913af07fc2055959e5ab91
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801850
Reviewed-on: http://git-master/r/806192
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
71afbe484f gpu: nvgpu: fuse read to boot in SECURE mode 
-Read fuse to boot in secure/production
 mode else non sercure mode.

Bug N/A

Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/791323
Reviewed-on: http://git-master/r/806191
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Robert Morell
e7ab0321d3 gpu: nvgpu: gp10b: Correct C097_SET_GO_IDLE_TIMEOUT offset 
Bug 1678603

Change-Id: I1c2c3c9395e068fabf554779ded6f0f536622c90
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/792831
Reviewed-on: http://git-master/r/806187
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
cc182623ab gpu: nvgpu: gp10b: Disable deep binning 
Disable deep binning by default.

Change-Id: I75da95984ac314015c6927e099a3eaa37fcc26fc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/790403
Reviewed-on: http://git-master/r/806186
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
c54ebdd78a gpu: nvgpu: gp10b: Implement NVC0_SET_GO_IDLE_TIMEOUT 
Bug 1678603

Change-Id: Ib8fb09dace864567b1ce574c216a584831723684
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/790402
Reviewed-on: http://git-master/r/806185
 2016-12-27 15:22:07 +05:30
Sami Kiminki
48cbfac597 gpu: nvgpu: Add CDE scatter buffer code for GP10B 
Add GP10B-specific code for populating the scatter buffer. Essentially,
this enables the use of SMMU bypass mode with 4-kB page compression.

Bug 1604102

Change-Id: Ic586e2f93827b9aa1c7b73b53b8f65d518588c26
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/789434
Reviewed-on: http://git-master/r/806184
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
5df1bc28b3 gpu: nvgpu: gp10b: Choose netlist A 
Force usage of netlist slot A.

Change-Id: Ib507b0e0c7ff6d0dbb43f91b6c7264424975d681
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/789060
Reviewed-on: http://git-master/r/806183
 2016-12-27 15:22:07 +05:30
Deepak Nibade
17bc6e6457 gpu: nvgpu: fix sparse warning 
Fix below sparse warning by declaring gp10b_write_dmatrfbase()
as static

kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol
'gp10b_write_dmatrfbase' was not declared. Should it be static?

Bug 200088648

Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/801213
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
cc1b124d5a gpu: nvgpu: HAL to write DMATRFBASE 
- Must write DMATRFBASE1 to 0 whenever
  DMATRFBASE is written.

Bug 200137618

Change-Id: Id8526d1bafbd116ffc4d8018983791fe9e9fa604
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798780
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
83955e553c gpu: nvgpu: priv load for gpccs load. 
- clear mask to load gpcss with priv load.

Bug n/a

Change-Id: I21522bda83c4dd5c665d47ae334b9fed5cb8ec74
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798406
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30