Commit Graph

8 Commits

Author SHA1 Message Date
Philip Elcan
27eb393cc8 gpu: nvgpu: acr: cast sizeof assignment to u32's
MISRA 10.3 prohibits implicit assignment of objects to a narrower or
different essential type. This change addresses cases in the ACR code
where the u64 result of sizeof() is being assigned to a u32.

JIRA NVGPU-1008

Change-Id: Id4ccb0ef6c0fd9872c4e8cb7ede736e9ae326c6c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959636
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-11-30 16:34:16 -08:00
Seema Khowala
ba0d76189e gpu: nvgpu: address alloc_blob_space physically
Add NVGPU_DMA_PHYSICALLY_ADDRESSED flag for blob_space.

Bug 2422486

Change-Id: I44347430ee03b473875d8e49500a08c40ef9194f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1962057
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-30 14:13:47 -08:00
Philip Elcan
d740a9cec6 gpu: nvgpu: acr: cast assignments of sizeof to u32
This change fixes a number of This is a MISRA 10.3 rule violation due to
the implicit casts of sizeof() to u32's. This change adds u32 casts to
each of these violations. This should be safe because a 4GB type size
would be very unlikely in this driver.

JIRA NVGPU-1008

Change-Id: I359cda790278af6e6dfaec8599e2b02c11670fc2
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959428
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-28 14:34:21 -08:00
Sagar Kamble
fd332ca6b4 gpu: nvgpu: s/*_flcn_*/*_falcon_*
There is mixed usage of falcon & flcn in function and data types.
Lets update all with "falcon" for consistency with file names.

JIRA NVGPU-1459

Change-Id: I02dbc866ce2cca009f2e8b87cfe11a919ec10749
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1953793
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-11-21 23:04:36 -08:00
Amurthyreddy
23f35e1b2f gpu: nvgpu: MISRA 14.4 bitwise operation as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the result of a bitwise operation is used as a
boolean in the controlling expression of if and loop statements.

JIRA NVGPU-1020

Change-Id: I6a756ee1bbb45d43f424d2251eebbc26278db417
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936334
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-13 09:45:25 -08:00
Scott Long
9834fb40fe gpu: nvgpu: nvgpu_memcpy changes to acr code
MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.

To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.

This change switches non-offending memcpy usage in acr code
over to to use nvgpu_memcpy() with appropriate casts applied
to maintain consistency within nvgpu.

JIRA NVGPU-849

Change-Id: I55bca75b816d103d70d5825ffa633f64d9379add
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946267
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2018-11-12 22:33:48 -08:00
smadhavan
f1747cbcd1 gpu: nvgpu: Fix MISRA rule 8.3 violations
MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the parameter as required.

JIRA NVGPU-847

Change-Id: I3f7280b0e4c21b1c2d70fd7f899cf920075f87a3
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1927103
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-12 22:33:18 -08:00
Terje Bergstrom
f00d9ca1aa gpu: nvgpu: Move pmu HAL files to common/pmu
Move PMU and ACR HAL source code files to live under common/pmu. Also
update the #include paths and delete unnecessary #include dependencies.

JIRA NVGPU-961

Change-Id: I29a220bce6de0a46b6a5fe8ff7f9dc4d67395348
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1935626
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-08 20:04:06 -08:00