gpu: nvgpu: address alloc_blob_space physically

Add NVGPU_DMA_PHYSICALLY_ADDRESSED flag for blob_space.

Bug 2422486

Change-Id: I44347430ee03b473875d8e49500a08c40ef9194f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1962057
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2018-11-29 11:32:41 -08:00
committed by mobile promotions
parent 94d4a42d10
commit ba0d76189e
3 changed files with 3 additions and 16 deletions

View File

@@ -333,7 +333,8 @@ int gm20b_alloc_blob_space(struct gk20a *g,
{
int err;
err = nvgpu_dma_alloc_sys(g, size, mem);
err = nvgpu_dma_alloc_flags_sys(g,
NVGPU_DMA_PHYSICALLY_ADDRESSED, size, mem);
return err;
}

View File

@@ -53,18 +53,6 @@
/*Forwards*/
int gv11b_alloc_blob_space(struct gk20a *g,
size_t size, struct nvgpu_mem *mem)
{
int err;
gv11b_dbg_pmu(g, "alloc blob space: NVGPU_DMA_FORCE_CONTIGUOUS");
err = nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_FORCE_CONTIGUOUS,
size, mem);
return err;
}
void gv11b_setup_apertures(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
@@ -171,7 +159,7 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
gv11b_acr_default_sw_init(g, &acr->acr);
acr->get_wpr_info = gm20b_wpr_info;
acr->alloc_blob_space = gv11b_alloc_blob_space;
acr->alloc_blob_space = gm20b_alloc_blob_space;
acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr;
acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode;
acr->acr_fill_bl_dmem_desc =

View File

@@ -28,8 +28,6 @@ int gv11b_bootstrap_hs_flcn(struct gk20a *g);
int gv11b_init_pmu_setup_hw1(struct gk20a *g,
void *desc, u32 bl_sz);
void gv11b_setup_apertures(struct gk20a *g);
int gv11b_alloc_blob_space(struct gk20a *g, size_t size,
struct nvgpu_mem *mem);
void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr,