Add NVGPU_SUPPORT_COMPRESSION to indicate if compression feature is
supported in nvgpu. If not, set cbc.init, cbc.ctrl and
cbc.alloc_comptags hals to NULL.
Add corresponding GPU characteristics flag and IOCTL mapping to sync
compression support status with nvrm_gpu.
JIRA NVGPU-4666
Change-Id: I2e685688ddac592b3bb918ee70c82ea5524d695a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2338926
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- "include/trace/events/gk20a.h" file was having GPL2 license
(which should not used for QNX code). This file was used for
compiling linux userspace driver("libnvgpu-drv.so") and was used for
unit testing on QNX.
- This patch removes stubs in "include/trace/events/gk20a.h" file.
(which were used for linux userspace driver.)
- For QNX driver, "nvgpu_rmos/trace/events/gk20a.h" was used.
This patch moves that file to "include/nvgpu/posix/trace_gk20a.h" and
does relevant license change. This same file will be used for linux
userspace driver.
- This patch also creates a new file "include/nvgpu/trace.h" which
selects proper trace file depending on the config.
Bug 2802414
Change-Id: Icdfb251e5698073f986753a969e804161af3ecc5
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2286388
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To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute
on different hardware resources.
This feature requires a change in software to make it possible
to modify the virtual SM id to TPC mapping across mission and
redundant contexts.
This CL adds only SM diversity flags which are exposed to
its clients through ioctl/devctl interfaces.
Actual virtual SM id to TPC mapping implementation
will be part of upcoming patch sets.
Added NvGpu CFLAGS to identify the safety build
"CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY"
JIRA NVGPU-4133
Change-Id: I5a18256780e6726e399e39c1c8d155d2ef07d7bd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250461
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
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Several of the nvgpu driver capabilities will be disabled in the reduced
version. To know the version of the nvgpu driver we introduce a new
global characteristic flag NVGPU_DRIVER_REDUCED_PROFILE.
JIRA NVGPU-3062
Change-Id: I93c76df1110c24ea0055c77d332fe297d56db65d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108143
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Remove __packed attributes from structs where the binary layout does
not change by the removal. That makes their use easier in userspace,
as __packed also changes the alignment rules of the structs and their
members.
With certain compilers, the packed alignment breaks code that assigns
pointers or C++ references to the struct field members. This is
because the modern C/C++ specifications require that pointer values
are aligned by the pointed type. But if the struct is packed, the
fields are no longer guaranteed to be naturally aligned by the language,
even if they are in practice.
Bug 1777616
Bug 1902982
JIRA GCSS-289
Change-Id: I30af9ee2f24a9c08dc591d3de012280f6e7d0cb2
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035940
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add new variable in nvgpu_as_map_buffer_ex_args for app
to specify the platform atomic support for the page.
When platform atomic attribute flag is set, pte memory
aperture is set to be coherent type.
renamed nvgpu_aperture_mask_coh -> nvgpu_aperture_mask_raw
function.
bug 200473147
Change-Id: I18266724dafdc8dfd96a0711f23cf08e23682afc
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012679
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Commit eb887094e4 ("gpu: nvgpu: nvgpu locks to vanilla Linux locks")
removed all use of nvgpu/linux/lock.h from nv-p2p.h, but didn't remove
the inclusion of that file. Remove the inclusion so that nv-p2p.h doesn't
require locnvgpu/linux/lock.h to be present.
Bug 200438879
Bug 1940058
Change-Id: I1bb3b2e5e5c8bd56d1e48f255c0675493953ba07
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2020685
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Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS to debugger node, to
install/uninstall a buffer for cycle stats.
Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT to debugger
node, to attach/flush/detach a buffer for Mode-E streamout.
Those ioctls will apply to the first channel in the debug session.
Bug 200464613
Jira NVGPU-1442
Change-Id: I0b96d9a07c016690140292fa5886fda545697ee6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2002060
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Replace nvgpu locks to vanilla Linux locks. For the custom kernel
driver when they include nv-p2p.h, nvgpu/linux/lock.h will not be
available because nvgpu/linux/lock.h is not copied to
/usr/src/kernel_header_file.
Bug 200438879
Change-Id: I55b52c6f791970650388b7d51c4d30b5fe75bbb8
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997950
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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NVGPU_CTXSW_IOCTL_RING_SETUP can be used to setup a custom ring buffer
and it accepts size via arguments. nvgpu driver will return an error
if size requested is greater than 128 * 4096 but this value is hardcoded
and not exposed anywhere.
Add characteristics field in nvgpu.h to expose this size so that corresponding
nvrm_gpu API can use it.
Bug 2169674
Change-Id: Icf9465d4eec6ba3a307ea9490bd5da563944e4f6
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967596
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Add a flag that let's userspace enable the unified VM functionality
on a selective bassis. This feature is working for all cases except
a single MODS trace. This will allow test coverage to be selectively
added in certain userspace tests as well to help prevent this feature
from bit rotting (as it has historically done).
Also update the unit test for the page table management in the GMMU
to reflect this new flag. It's been set to false since the target
platform for safety is currently not using unified address spaces.
Bug 200438879
Change-Id: Ibe005472910d1668e8372754be8dd792773f9d8c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951864
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Add a flag to nvgpu_gpu_characteristics to expose FECS tracing capability to
userspace.
This is required for adding nvrm_gpu APIs for CTXSW set of IOCTLs which were
requested in several bugs.
nvrm_gpu APIs would query this flag to check the availability of IOCTLs.
Bug 2169678
Bug 2169677
Bug 2169675
Bug 2169674
Bug 2169673
Bug 2168342
Change-Id: Ie6ba80a4144637546b97fa93baae67b8d0c4d425
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950559
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in GPU specific files.
JIRA NVGPU-1036
Change-Id: Iefadc38bdbea4f02de3c24b6ad1c71d6eb0af4bd
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929903
GVS: Gerrit_Virtual_Submit
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in OS/Linux interface.
JIRA NVGPU-1036
Change-Id: I39b20f1d0e1a1da56d452f2c3d5ee049666cefe8
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Import userd and gpfifo buffers from userspace if provided via
NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token
(i.e., the hw channel id) to userspace.
To keep the buffers alive, store their dmabuf and attachment/sgt handles
in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for
buffers that are mainly in kernel use. The buffers are freed via a new
API in the os_channel interface.
Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the
usermode gpfifo buffer.
Bug 200145225
Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795821
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For a long time now, the ALLOC_GPFIFO_EX channel IOCTL has done much
more than just gpfifo allocation, and its signature does not match
support that's needed soon. Add a new one called SETUP_BIND to hopefully
cover our future needs and deprecate ALLOC_GPFIFO_EX.
Change nvgpu internals to match this new naming as well.
Bug 200145225
Change-Id: I766f9283a064e140656f6004b2b766db70bd6cad
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1835186
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NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was
resident in engine or not.
Regops are broken down into batches of 128 and each batch is executed
together. Since there only 32 bits were available in IOCTL args, returning
is ctx was resident isn't possible for all batches.
Hence return if the ctx was resident for the first batch.
Bug 200445575
Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812975
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Add READ_SM_ERROR IOCTL support to TSG level.
Moved the struct to save the sm_error details
from gr to tsg as the sm_error support is context
based, not global.
Also corrected MISRA 21.1 error in header file.
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and
nvgpu_dbg_gpu_ioctl_read_single_sm_error_state
functions are modified to use the tsg struct
nvgpu_tsg_sm_error_state.
Bug 200412642
Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794856
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is
added to dbg session.
Currently support SM_EXCEPTION_TYPE_MASK_FATAL type
If this type is set then the code will skip RC recovery,
instead trigger CILP preemption.
bug 200412641
JIRA NVGPU-702
Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729792
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