Konsta Hölttä
1117ea1286
gpu: nvgpu: ce: check address ranges before exec
...
The source and destination addresses are masked to low 40 bits only.
Make sure that the input params don't cross that; it would mean a bug
somewhere in the caller side. Silently truncating values could cause
unexpected behaviour, but no device even has that much memory.
Also rename the src_buf and dst_buf to src_paddr and dst_paddr to
emphasize that the addresses are gpu physical.
Jira NVGPU-5172
Change-Id: I30653bf93791517991d04e4ba43220b5b541f581
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2402031
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
a54e4f1d74
gpu: nvgpu: ce: use clear upper bound for op size
...
The copyengine code to do big transfers or memsets supports a 64-bit
size. Each copy is done as a rectangle with either side being at most
2GB, so a size that does not align nicely is split into multiple ops. It
turns out that there are at most two of these ops, so structure the code
to not loop but do two ops explicitly.
The first copyengine operation works with the first chunk that is less
than two gigabytes long. That leaves the remaining size to be a multiple
of two gigabytes, so it's sufficient to do just another operation as a
2D rectangle whose width is two gigabytes; the remaining size determines
the height, i.e. the number of two-gig lines.
The loop did just this already, but now with at most two operations per
submit the required pushbuf length is seen more easily from the code.
Jira NVGPU-5172
Change-Id: I6bca3b1204db3b79e131898c07018a1337d85774
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2402028
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
4351978013
gpu: nvgpu: ce: make payload param u32
...
The payload word used for copyengine memsets is written to an u32
buffer, so use the correct type from the beginning.
Jira NVGPU-5172
Change-Id: Id813e042b609cb9d0705ba32d3cc03351bded413
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2402027
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2020-12-15 14:13:28 -06:00
Debarshi Dutta
17486ec1f6
gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
...
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel
Jira NVGPU-3248
Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2112424
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2019-05-06 02:56:53 -07:00
Thomas Fleury
1160f083d4
gpu: nvgpu: move ce code to common/ce and hal/ce
...
Merged gk20a_ce_delete_context and gk20a_ce_delete_context_priv.
Renamed
- gk20a_init_ce_support -> nvgpu_ce_init_support
- gk20a_ce_destroy -> nvgpu_ce_destroy
- gk20a_ce_suspend -> nvgpu_ce_suspend
- gk20a_ce_create_context -> nvgpu_ce_create_context
- gk20a_ce_delete_context -> nvgpu_ce_delete_context
- gk20a_ce_execute_ops -> nvgpu_ce_execute_ops
- gk20a_ce_prepare_submit -> nvgpu_ce_prepare_submit
- gk20a_ce_put_fences -> nvgpu_ce_put_fences
- gk20a_ce_delete_gpu_context -> nvgpu_ce_delete_gpu_context
- gk20a_ce_get_method_size -> nvgpu_ce_get_method_size
- gk20a_gpu_ctx -> nvgpu_ce_gpu_ctx
- gk20a_gpu_ctx_from_list -> nvgpu_ce_gpu_ctx_from_list
- gk20a_ce_app -> nvgpu_ce_app
- gk20a_ce_debugfs_init -> nvgpu_ce_debugfs_init
- gk20a_get_valid_launch_flags -> nvgpu_ce_get_valid_launch_flags
- gk20a_ce2_isr -> gk20a_ce2_stall_isr
- gp10b_ce_isr -> gp10b_ce_stall_isr
- gv11b_ce_isr -> gv11b_ce_stall_isr
Inlined
- ce*_nonblockpipe_isr
- ce*_blockpipe_isr
- ce*_launcherr_isr
Added ce_priv.h for ce private definitions.
Moved files to common/ce and hal/fifo/ce
- ce2.c -> common/ce2/ce.c
- ce2_gk20a.c -> hal/ce/ce2_gk20a.c
- ce2_gk20a.h -> hal/ce/ce2_gk20a.h
- ce_gp10b.c -> hal/ce/ce_gp10b.c
- ce_gp10b.h -> hal/ce/ce_gp10b.h
- ce_gv11b.c -> hal/ce/ce_gv11b.c
- ce_gv11b.h -> hal/ce/ce_gv11b.h
Updated makefiles and #include directives
Jira NVGPU-1992
Change-Id: Ia6064bf51b7a254085be43a112d056cb6fb6c3b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2093503
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2019-04-19 13:55:11 -07:00
