-Add check for ECC parity errors in IMEM, DMEM, EMEM, DCLS, REG
for ACR running in GSP engine.
The EXTIRQ3 external interrupt is set from ACR pointing towards host.
-Add function to check error type when ACR or Bootrom execution fails
and report accordingly to SDL with relevant error codes.
This is a part of HSI safety requirements.
Bug 3564039
Jira NVGPU-8108
Change-Id: I65407371f7a1d1ba50a10bdf443ef6b903eeaa36
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2678100
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Separated gsp unit into three unit:
- GSP unit which holds the core functionality of GSP RISCV core,
bootstrap, interrupt, etc.
- GSP Scheduler to hold the cmd/msg management, IPC, etc.
- GSP Test to hold stress test ucode specific support.
NVGPU-7492
Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I12340dc776d610502f28c8574843afc7481c0871
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2660619
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Changes:
- This change will only init gsp software
state, nvgpu_gsp_bootstrap need to be called.
- CONFIG_NVGPU_GSP_SCHEDULER flag is created to
compile out the gsp scheduler code when needed.
- Created GSP engine reset which is needed when
ACR completed execution and need to load gsp fw.
NVGPU-6783
Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I2ce43e512b01df59443559eab621ed39868ad158
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554267
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Added the following HALs
- ramin.base_shift
- ramin.alloc_base
Use above HALs in mm, instead of using hw definitions.
Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits
Added missing #include for <nvgpu/mm.h>
Jira NVGPU-3015
Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
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Currently SEC2/GSP uses the PMU VM space for memory access which adds
dependency on PMU, So, created separate VM space for SEC2/GSP of
size 32MB as currently used for ucode handling by these units.
SEC2/GSP VM space allocation happens if NVGPU_SUPPORT_SEC2_VM/
NVGPU_SUPPORT_GSP_VM enable flags set.
JIRA NVGPU-2910
Change-Id: I4dfe50a1c0adb7e83379bf6c15343fe57ff44c38
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077596
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