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gpu: nvgpu: Deleting GSP HAL's GV100 support

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-Deleting GV100 from GSP HAL as GV100 is not supported
 anymore.
-Renamed all GSP related code to tu104 to deprecate GV100
 GSP support

JIRA NVGPU-3243

Change-Id: I2ce321ee045797133456d04871a3d7bb8a223911
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168245
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-08-05 15:47:33 +05:30
committed by mobile promotions
parent 5f8fb9f41a
commit 82c5ff8712
6 changed files with 19 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/nvgpu-hal-new.yaml
View File

@@ -340,8 +340,8 @@ fuse:
gsp:
safe: no
sources: [ hal/gsp/gsp_gv100.c,
hal/gsp/gsp_gv100.h ]
sources: [ hal/gsp/gsp_tu104.c,
hal/gsp/gsp_tu104.h ]
mm:
safe: yes

2
drivers/gpu/nvgpu/Makefile
View File

@@ -286,7 +286,7 @@ nvgpu-y += \
hal/nvlink/minion_tu104.o \
hal/nvlink/link_mode_transitions_gv100.o \
hal/nvlink/link_mode_transitions_tu104.o \
hal/gsp/gsp_gv100.o \
hal/gsp/gsp_tu104.o \
hal/sec2/sec2_tu104.o \
hal/sync/sema_cmdbuf_gk20a.o \
hal/sync/sema_cmdbuf_gv11b.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -614,7 +614,7 @@ srcs += common/sec2/sec2.c \
hal/netlist/netlist_tu104.c \
hal/nvdec/nvdec_gp106.c \
hal/nvdec/nvdec_tu104.c \
hal/gsp/gsp_gv100.c \
hal/gsp/gsp_tu104.c \
hal/sec2/sec2_tu104.c \
hal/pramin/pramin_gp10b.c \
hal/pramin/pramin_gv100.c \

10
drivers/gpu/nvgpu/hal/gsp/gsp_gv100.c → drivers/gpu/nvgpu/hal/gsp/gsp_tu104.c
View File

@@ -27,11 +27,11 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
#include "gsp_gv100.h"
#include "gsp_tu104.h"
#include <nvgpu/hw/gv100/hw_pgsp_gv100.h>
#include <nvgpu/hw/tu104/hw_pgsp_tu104.h>
int gv100_gsp_reset(struct gk20a *g)
int tu104_gsp_reset(struct gk20a *g)
{
if (g->is_fusa_sku) {
return 0;
@@ -46,7 +46,7 @@ int gv100_gsp_reset(struct gk20a *g)
return 0;
}
void gv100_gsp_flcn_setup_boot_config(struct gk20a *g)
void tu104_gsp_flcn_setup_boot_config(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
u32 inst_block_ptr;
@@ -102,7 +102,7 @@ void gv100_gsp_flcn_setup_boot_config(struct gk20a *g)
gk20a_writel(g, pgsp_falcon_engctl_r(), data);
}
u32 gv100_gsp_falcon_base_addr(void)
u32 tu104_gsp_falcon_base_addr(void)
{
return pgsp_falcon_irqsset_r();
}

12
drivers/gpu/nvgpu/hal/gsp/gsp_gv100.h → drivers/gpu/nvgpu/hal/gsp/gsp_tu104.h
View File

@@ -20,11 +20,11 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GSP_GV100_H
#define GSP_GV100_H
#ifndef GSP_TU104_H
#define GSP_TU104_H
int gv100_gsp_reset(struct gk20a *g);
void gv100_gsp_flcn_setup_boot_config(struct gk20a *g);
u32 gv100_gsp_falcon_base_addr(void);
int tu104_gsp_reset(struct gk20a *g);
void tu104_gsp_flcn_setup_boot_config(struct gk20a *g);
u32 tu104_gsp_falcon_base_addr(void);
#endif /*GSP_GV100_H */
#endif /* GSP_TU104_H */

8
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -145,7 +145,7 @@
#include "hal/pmu/pmu_tu104.h"
#include "hal/falcon/falcon_gk20a.h"
#include "hal/nvdec/nvdec_tu104.h"
#include "hal/gsp/gsp_gv100.h"
#include "hal/gsp/gsp_tu104.h"
#include "hal/perf/perf_gv11b.h"
#ifdef CONFIG_NVGPU_DGPU
#include "hal/sec2/sec2_tu104.h"
@@ -1423,9 +1423,9 @@ static const struct gpu_ops tu104_ops = {
},
#endif
.gsp = {
.falcon_base_addr = gv100_gsp_falcon_base_addr,
.falcon_setup_boot_config = gv100_gsp_flcn_setup_boot_config,
.gsp_reset = gv100_gsp_reset,
.falcon_base_addr = tu104_gsp_falcon_base_addr,
.falcon_setup_boot_config = tu104_gsp_flcn_setup_boot_config,
.gsp_reset = tu104_gsp_reset,
},
.top = {
.device_info_parse_enum = gm20b_device_info_parse_enum,