3 Commits

Author	SHA1	Message	Date
Nitin Kumbhar	c69c5a7a60	gpu: nvgpu: use safe ops in ALIGN and ALIGN_MASK ... Shortcomings of ALIGN macros: - ALIGN_MASK down aligns when there is an wrapping/overflow instead of throwing an error. This can affect the size assumptions. - Alignment a's check will be bypassed when ALIGN_MASK is directly used. Fix these issues by 1) adding compile time error for non-unsigned type arguments 2) using unsigned type safe ops for addition and subtraction. Also, change users of ALIGN to pass unsigned types only. JIRA NVGPU-3515 Jira NVGPU-3411 Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2128382 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-06-28 08:56:27 -07:00
Vedashree Vidwans	c3f7d9a3b0	gpu: nvgpu: fix MISRA 17.7 in common.sec2.allocator ... MISRA Rule 17.7 doesn't allow return value of a function to be ignored. This patch checks return value of nvgpu_allocator_init function and returns error to the sec2_process_init_msg() function. Jira NVGPU-3321 Change-Id: Ie3eb1b5f9312e178f8f3e6de310d768c3ac3e220 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123221 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-05-22 16:44:59 -07:00
Sagar Kamble	d7bdca94d8	gpu: nvgpu: move sources to sec2 ipc element ... SEC2 command, message, queues, sequences are part of SEC2's infrastructure for IPC. Create common/sec2/ipc folder and move all these sources there. JIRA NVGPU-2075 Change-Id: Id6d7a31422fae835ec669c8ea48b3f63b9dffe24 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085756 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-10 09:27:42 -07:00