A last minute fix in the runlist construction code rework reorganized
the order such that the ringbuf list starts with the highest level, not
lowest. Some tests were not updated though. Adjust comments and naming
to indicate what the tests really do, and add one more test to cover all
branches in the interleaved construction logic.
Jira NVGPU-1174
Change-Id: If608a35be2c5cf8f400df6673cd10c983ab91845
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975379
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Remove gp106 and add gv100 unit test
This is as a part of removing gp106 support
This adds testing for gv100 to the fuse unit test
Removes check_sec/non_sec as they are not used
Removes delta SRAM fuse as they are not present in GV100
Bug 200457373
Change-Id: I9bb4b714500eae01d0df00bb9f6842d4d4fbfd12
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1960034
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This unit test verifies that the PD cache is capable of packing
multiple PD allocations into a single page. The verification works
by using the DMA fault injection method to prevent more than one
DMA alloc from happening in the pd_cache code.
If an OOM error is detected by the pd_cache code before the max
number of PDs per page is allocated by the pd_cache then there's
a failure in the packing code.
The correct number of PDs per page is easy to calculate: it's
just PAGE_SIZE / pd_size.
JIRA NVGPU-1323
Change-Id: I2c5b58ecf32da48d503c576012d9e564a270144c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970876
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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There were several places were nvgpu_mem structs were declared on the
stack and not initialized. Some fields could be used erroneously by
underlying APIs.
To allow the initialization of an array of nvgpu_mem in
test_dma_alloc_fi_delayed_enable(), the array length had to be changed
from a const to a macro.
JIRA NVGPU-1563
Change-Id: I6c23445af7d932710898df2e23a8fd892bee77b3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967966
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add a flag that let's userspace enable the unified VM functionality
on a selective bassis. This feature is working for all cases except
a single MODS trace. This will allow test coverage to be selectively
added in certain userspace tests as well to help prevent this feature
from bit rotting (as it has historically done).
Also update the unit test for the page table management in the GMMU
to reflect this new flag. It's been set to false since the target
platform for safety is currently not using unified address spaces.
Bug 200438879
Change-Id: Ibe005472910d1668e8372754be8dd792773f9d8c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951864
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The pd_cache header declarations were oriignally part of the
gmmu.h header. This is not good from a unit isolation perspective
so this patch moves all the pd_cache specifics over to a new
header file: <nvgpu/pd_cache.h>.
Also a couple of static inlines that were possible when the code
was part of gmmu.h were turned into real, first class functions.
This allowed the pd_cache.h header to not include the gmmu.h
header file.
Also fix an issue in the nvgpu_pd_write() function where the data
was being passed as a size_t for some reason. This has now been
changed to a u32.
JIRA NVGPU-1444
Change-Id: Ib9e9e5a54544de403bfcd8e11c30de05721ddbcc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966352
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This reverts commit 15603b9fd5.
Causes a build break in the PD cache unit test. Not sure how this
passed GVS - must have been a race or something? Unclear.
Change-Id: Ia484a801d098d69441326fa1dd40a1c86e2e23ce
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966335
The pd_cache header declarations were originally part of the
gmmu.h header. This is not good from a unit isolation perspective
so this patch moves all the pd_cache specifics over to a new
header file: <nvgpu/pd_cache.h>.
Also a couple of static inlines that were possible when the code
was part of gmmu.h were turned into real, first class functions.
This allows the pd_cache.h header to not include the gmmu.h
header file.
Also fix an issue in the nvgpu_pd_write() function where the data
was being passed as a size_t for some reason. This has now been
changed to a u32.
JIRA NVGPU-1444
Change-Id: Iead9a0d998396d2289ffcb3b48765d770400397b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965271
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Split the nvgpu_sgt code out from the nvgpu_mem code. Although the
two chunks of code are related the SGT code is distinct and as
such should be its own unit. To do this a new source file has been
added - nvgpu_sgt.c - which contains all the nvgpu_sgt common APIs.
These are the facade APIs to abstract the actual details of how any
given nvgpu_sgt is actually implemented.
An abstract unit - nvgpu_sgt_os - was also defined. This unit
exists solely for the nvgpu_sgt unit to call so that the OS
specific nvgpu_sgt_os_create_from_mem() API can be moved from the
common nvgpu_sgt unit. Note this also updates the name of what the
OS specific units are expected to call. Common code may still use
the generic nvgpu_sgt_create_from_mem() API.
JIRA NVGPU-1391
Change-Id: I37f5b2bbf9f84c0fb6bc296c3e04ea13518bd4d0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946012
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This unit test covers the page_table map/unmap logic as well
as low level PDE/PTE handling.
This patch contains a first phase aiming to cover most
functionality and code coverage but it does not cover
most error handling cases nor formal requirements.
JIRA NVGPU-907
Change-Id: I3b63cfce6cee27d01e1ef54c763560a542992d33
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950974
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add a unit test to cover the pd_cache unit. This unit is
responsible for maintaining the page directory allocations.
It's effectively a DMA slab allocator since we want to be
able to pack multiple sub page sized page directories into
a single page.
JIRA NVGPU-1323
Change-Id: If65a803cf2ee5af9938668958b9353d50b2e98f9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1942248
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This adds testing for gp106 to the fuse unit test.
This provides 98% code coverage and 94% branch coverage for this
device/module. The missing coverage consists of 2 redundant case/default
statements that are checked previously in the same function.
JIRA NVGPU-938
Change-Id: I04872824204fe6a0e8fa0275726d372892fc78cf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943387
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This adds the initial unit test for the fuse module and testing for
gp10b. It verifies the exposed APIs for this device in the fuse module.
To allow the hal_init to pass before the HAL for
read_gcplex_config_fuse() can be overridden, the default behavior of the
POSIX implementation for nvgpu_tegra_fuse_read_gcplex_config_fuse() is
changed.
This provides 100% code and branch coverage for this unit/device.
JIRA NVGPU-938
Change-Id: I9efa8080c12ace637581c77aa35aab3f86a94760
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943385
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We will need to organize the unit tests in order to keep the
units/ directory managable.
The basic idea here is to mirror the common/ structure in
nvgpu proper under units/. There's one additrion at the
moment though: posix. This is for posix environment related
tests.
Also added a fix for the runlist unit test. Add it to the
tmake sources and move the nvgpu-runlist/ directory to just
runlist/.
Change-Id: I1f4163d0e33c3af70376cfeb3441d277d559e05a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1935710
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This unit test covers the nvgpu allocator high level logic for
calling nvgpu allocator imlementation routines. The nvgpu_allocator
code is generally very simple.
This gets to >90% coverage of the module. Once the fault injection
code is merged the failure path after nvgpu_mutex_init() will also
be coverable.
JIRA NVGPU-903
Change-Id: I7e180da9cbc518b6568c240fd5e67a233b17edc6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1927642
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
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The template tmake makefile for the unit test shared object interface
was using a relative path based on the component to find the common
export file. This uses a path relative to the project source path. This
allows multi-level directories for the unit tests (e.g.
../units/mm/nvgpu_allocator/).
Change-Id: Iff8d6419eec9fe8877f5ce8111a6045a10289dc9
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930006
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a unit test to do sanity checks for the environment. These
checks currently include:
- Size of types (f.e. u32 is really 4 bytes)
- Signedness of types (u32 is really unsigned)
- Endianness check
- Pointers fit in u64s
Note: the endianness check does not fail for either detected
endianness. It just prints the determined endianness. The exception
to this is if the check itself is broken and does not successfully
determine what endianness the underlying machine is. In that case
the test fails. Unless the underlying architure is a so called
middle endian machine something is horribly wrong.
We will determine what to actually do about this endianness
check once we determine what we need to do with BIOS fields,
etc. We proabbly don't really care what the machine endianness is
but we do need to make sure that we access data that may not match
machine endianness correctly.
JIRA NVGPU-1039
Change-Id: I5be68cf4dcea87e9e746262fcc0372380ef57df4
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1816897
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a unit test to test the nvgpu-posix bitmap implementation. This
unit test aims to both verify the functionality of this low level
set of APIs and provide a reference for how to use the basic unit
test functionality.
JIRA NVGPU-525
Change-Id: Ide5263e5ce49f18f5f2a3d4a6f9e494395299386
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1695007
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add a super simple tiny test unit module to test the unit test
framework.
This unit test has a test that deliberately fails so it obviously
cannot be part of a real unit test run. Eventually this will have
to be removed or otherwise skipped.
JIRA NVGPU-525
Change-Id: I41532a85156445a778897bbc84bb5919deab56ae
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1687095
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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