-Moved bind fecs from work queue to init_gr_support.
-It makes all CPU->FECS communication to happen before
booting PMU, and after we boot PMU, only PMU talks to
FECS. So it removes possibility to race between CPU
and PMU talking to FECS.
Bug 200032923
Change-Id: I01d6d7f61f5e3c0e788d9d77fcabe5a91fe86c84
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/559733
Fixed sparse non static symbol warning by making the following symbol 'static':
- to_gk20a_sync_pt
- to_gk20a_timeline
Bug 200032218
Change-Id: Ie0310116aa1500ae8e4838b8a9ad4943a61cfc24
Signed-off-by: Amit Sharma <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/552052
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
gk20a_vm_map_buffer() used to ignore silently map requests for
non-dmabuf fd:s. Fix this by returning the error code from
dma_buf_get().
Bug 1566862
Change-Id: If01b03f43b67b17d9fb997d914db871520f50c6e
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Writing start bit twice can confuse falcon and
results in random behavior.
Bug 200040021
Change-Id: I62eb8e4632ac4fc471d931155471084ee0f9d0a4
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
gpu rail gating reference count is going wrong because
"can_railgate" is set to false during probe(). For rail-gating
to work no gpu re-work is needed and by default rail-gating
is enabled with INT_MAX delay.
Bug 200044987
Change-Id: I9367275cd18c34cb19a51193353585789ba44c03
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/556568
Reviewed-by: Mitch Luban <mluban@nvidia.com>
When validating buffers to be mapped, check that the buffer end does not
overflow over the virtual address node space.
Bug 1562361
Change-Id: I3c78ec7380584ae55f1e6bf576f524abee846ddd
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
-Change cde_buf to use writecombined cpu mapping.
-Since reading writecombined cpu data is still slow, avoid reads in
gk20a_replace_data by checking whether a patch overwrites a whole
word.
-Remove unused distinction between src and dst buffers in cde_convert.
-Remove cde debug dump code as it causes a perf hit.
Bug 1546619
Change-Id: Ibd45d9c3a3dd3936184c2a2a0ba29e919569b328
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/553233
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>
Using KEPLER_C for doing sync point increment has side effects.
It adds a SetObject method, which changes channel state that not all
user space accounts for.
Bug 1462255
Bug 1497928
Bug 1559462
Change-Id: I5c422ad8ca94fba15cad9bd232f7a10d94aa0973
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/554478
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
GK20A PMU is not supported in GPU client for virtualization. However,
to make native case and virtualization case can share same defconfig and
kernel image, we need to enable CONFIG_GK20A_PMU and
CONFIG_GK20A_DEVFREQ in defconfig. This commit changes to detect if we
should disable GK20A PMU support in run time.
Bug 200041597
Change-Id: I292c647303ed57af6faa1c5671037ca27b48e31e
Signed-off-by: Haley Teng <hteng@nvidia.com>
Reviewed-on: http://git-master/r/553653
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
When initializing fifo, we ignore several error conditions. Add
checks for them.
Change-Id: Id67f3ea51e3d4444b61a3be19553a5541b1d1e3a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553269
If engine status is in context switch in the fifo mmu fault handler,
dump falcon stats and gr stats for each engine.
Bug 1544766
Change-Id: Idfa9772b7e67072941144ac3bdd73e791fdc2b23
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/553205
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Implement empty or -ENOSYS functions for vgpu if
CONFIG_TEGRA_GR_VIRTUALIZATION is not enabled, and remove ifdefs around
the calling code.
Change-Id: Idc75c9bc486d661786bc222bd9e0380aa7766e78
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/552898
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Correct some old comments and remove uses of the BIT macro to make it
easier to sync this file to userspace.
Change-Id: Ie897fc73e28b8194e0c5357eef7ae233395e9ba3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/552916
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
At this stage, ctxsw is always in reset state, because we're powering GPU
up, or we have reset the whole GR partition. Remove the code to invoke a
second reset.
Fix waiting for FE idle. We should wait after each bundle, and break if any
iteration fails.
Change-Id: I0846f67c6d860a485dea62ff870deafe55a47365
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/552799
When calculating fractional divider in GPCPLL NA mode quantize voltage
before (used to do it after) applying DFS_COEFF, to follow h/w order.
Bug 1555318
Change-Id: I37be2bc73cd1f849695b94acc4ff21caf26e8b97
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/552741
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
The return value of gk20a_busy must be checked since it may not succeed
in some cases. Add the __must_check attribute that generates a compiler
warning for code that does not read the return value and fix all uses of
the function to take error cases into account.
Bug 200040921
Change-Id: Ibc2b119985fa230324c88026fe94fc5f1894fe4f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542552
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
- Removed unnecessary static "initialized" variable (sw_ready flag is
protecting from multiple initializations, anyway).
- Used max frequency at min voltage to set initial configuration of
GPCPLL in both NA and non-NA mode. For backward compatibility made
sure initial PLL output rate do not exceed 1/3 of VCO minimum.
Bug 1555318
Change-Id: If970c27442ea1109d4503a322998a6a26159c345
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/552370
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Expose a debugfs entry pmu_security. It allows checking if PMU was
booted in secure or non-secure mode.
Change-Id: Iea584b696440779bee0900edccabd4e5b2997805
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/552456
Move nvgpu ioctls from the many user space interface headers to a new
single nvgpu.h header under include/uapi. No new code or replaced names
are introduced; this change only moves the definitions and changes
include directives accordingly.
Bug 1434573
Change-Id: I4d02415148e437a4e3edad221e08785fac377e91
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542651
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
To help remove the nvhost dependency from nvgpu, rename ioctl defines
and structures used by nvgpu such that nvhost is replaced by nvgpu.
Duplicate some structures as needed.
Update header guards and such accordingly.
Change-Id: Ifc3a867713072bae70256502735583ab38381877
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542620
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
In preparation for GM20B GPCPLL NA data integration:
- Added VCO control initialization code (no data, yet)
- Replaced absolute safe margin with relative percentage
(preliminary 8%)
- Retrieved maximum safe frequency at minimum voltage from GPU DVFS
table, instead of hard-coded macro (also fix the name of the limit:
maximum instead of minimum)
- Updated comments
Bug 1555318
Change-Id: I49a7a90cc4bc29e181065ebd2cf9d214edae6465
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/542462
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Proper error number for invalid request number is EINVAL instead of
EFAULT, so change it in ioctl calls.
Change-Id: I8fddd34e012700550e9e30fe17ba7152b3a0417b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/542563
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change CDE swizzling shader kernel size to 8x8 to avoid waste with
relatively small surfaces.
Map compbit backing store and destination surface as cacheable.
Clean up kernel size calculation.
Bug 1546619
Change-Id: Ie97c019b4137d2f2230da6ba3034387b1ab1468a
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/501158
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>
Added configuration option to enable GM20b GPCPLL noise aware (NA)
mode. In this mode PLL output frequency is automatically adjusted when
GM20b voltage is fluctuating.
NA mode is disabled by default.
Bug 1555318
Change-Id: Ia9741fd02ddacaf4743e5397b729293fa5181f84
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/534079
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Added support for GM20b GPCPLL frequency change in NA mode outside of
bypass. In this case the respective PLL DVFS detection settings are
updated in flight. The implemented algorithm relies on characterization
providing two frequency limits at the same voltage: max frequency on
the F/V curve (Fmax@V) in NA mode with characterized DVFS coefficient,
and safe frequency under the curve when DVFS coefficient is zero
(Fsafe@V, which is effectively the same as Fmax@V in legacy/non-DVFS
mode).
Transition between two Fmax@V points on the curve includes:
- Lowering frequency to Fsafe@V for the minimum V of the transition
end-points
- Setting DVFS coefficient to zero
- Changing DVFS calibration point to the new voltage
- Setting DVFS coefficient characterized for the new voltage
- Setting final target frequency
Note that voltage is changed by Tegra SoC DVFS before (when voltage
increases), or after (whet voltage decreases) the above procedure.
This commit kept NA mode disabled.
Bug 1555318
Change-Id: Ib5620aaa113dc1caa69ecd402d9c6f68e39c472c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/501042
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Added support for GM20b GPCPLL dynamic ramp in NA mode that requires
ramping of both integer NDIV and fractional SDM_DIN controls. If NA
mode is enabled, dynamic ramp is used only for transition to / from
disabled state. PLL frequency in NA mode is still changed under bypass
only.
This commit kept NA mode disabled.
Bug 1555318
Change-Id: I91f5722a485d1b66b6113aa9c35a2fe36c38ea80
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/500637
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Added basic support for GM20b GPCPLL noise-aware(NA) mode. In this
mode PLL internal DVFS mechanism is engaged, and output frequency is
scaled with voltage automatically. The scaling coefficients in this
commit are preliminary, pending characterization.
If NA mode is enabled, any frequency change is done under PLL bypass,
with no dynamic ramp allowed.
This commit kept NA mode disabled.
Bug 1555318
Change-Id: I8d96a10006155635797331bae522fb048d3dc4a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499488
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Channel gpfifo cannot be submitted if the channel has no vm, so add a
check for it and bail out if no as is bound. Clean up other similar
checks too.
Change-Id: Ibb0fe08e44e34bbaaa00ebd02dce6cc4d93ca5d9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/538887
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
nvhost_sync_create_fence returns ERR_PTRs instead of NULLs on error;
check for its errors with IS_ERR.
Change-Id: I9752e0d8fa703b2872918b23721ae973be58bf35
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/533794
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Retrieve channel count from gm20b specific header instead of the
gk20a header. This increases channel count from 128 to 512.
Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500623
