gr_gv100_reset_hwpm_pmm_registers() writes a bunch of registers in
sys/gpc/fbp chiplets to reset perfmons. To ensure all the writes have
completed it is necessary to readback each chiplet's PRI fence register.
Add and use new HAL g->ops.priv_ring.read_pri_fence() to achieve this.
Implement the HAL for gv11b in new source code file
hal/priv_ring/priv_ring_gv11b.c.
Bug 2510974
Jira NVGPU-5360
Change-Id: If4dd61cb4265422e8c2d16884790eb0fe7f2c103
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2453631
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There were following stale hw header files as their source script
changes were not present. These still had the static inline
functions.
Deleted below files as they are not used:
gk20a/hw_pri_ringstation_fbp_gk20a.h
gp106/hw_gc6_gp106.h
Regenerated with updated script changes:
gv11b/hw_usermode_gv11b.h
JIRA NVGPU-3733
Change-Id: I40b79b43b7f085c01858f3584fcf2c8928d62d13
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152825
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add the YAML arch to the linux-nvgpu repo so that the arch and source
code can be kept entirely in sync.
When the YAML was in a separate repo it was too difficult to keep things
in sync. Based on this work the next steps are:
1. Gate compilation on no sources issues (missing or orphan source
files.
2. Perhaps use the arch to generate the Makefile.sources files.
JIRA NVGPU-3074
JIRA NVGPU-3075
Bug 2587555
Change-Id: Ic62be3e5e7ea1fb61ea50a2d611f905fa574988f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113154
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
