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gpu: nvgpu: ensure all perfmon writes are complete after reset

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gr_gv100_reset_hwpm_pmm_registers() writes a bunch of registers in
sys/gpc/fbp chiplets to reset perfmons. To ensure all the writes have
completed it is necessary to readback each chiplet's PRI fence register.

Add and use new HAL g->ops.priv_ring.read_pri_fence() to achieve this.

Implement the HAL for gv11b in new source code file
hal/priv_ring/priv_ring_gv11b.c.

Bug 2510974
Jira NVGPU-5360

Change-Id: If4dd61cb4265422e8c2d16884790eb0fe7f2c103
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2453631
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-09-21 12:19:16 +05:30
committed by Alex Waterman
parent 8c94013c4d
commit b23a114c63
16 changed files with 225 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/nvgpu-gpu_hw.yaml
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@@ -170,6 +170,7 @@ headers:
include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h,
include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h,
include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h,
include/nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h,
include/nvgpu/hw/gv11b/hw_proj_gv11b.h,
include/nvgpu/hw/gv11b/hw_pwr_gv11b.h,
include/nvgpu/hw/gv11b/hw_ram_gv11b.h,
@@ -209,6 +210,7 @@ headers:
include/nvgpu/hw/tu104/hw_pri_ringmaster_tu104.h,
include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h,
include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h,
include/nvgpu/hw/tu104/hw_pri_ringstation_fbp_tu104.h,
include/nvgpu/hw/tu104/hw_proj_tu104.h,
include/nvgpu/hw/tu104/hw_psec_tu104.h,
include/nvgpu/hw/tu104/hw_pwr_tu104.h,

4
arch/nvgpu-hal-new.yaml
View File

@@ -88,7 +88,9 @@ priv_ring_fusa:
priv_ring:
safe: no
owner: Seema K
sources: [ hal/priv_ring/priv_ring_gm20b.c ]
sources: [ hal/priv_ring/priv_ring_gm20b.c,
hal/priv_ring/priv_ring_gv11b.c,
hal/priv_ring/priv_ring_gv11b.h ]
ptimer_fusa:
safe: yes

3
drivers/gpu/nvgpu/Makefile
View File

@@ -363,7 +363,8 @@ nvgpu-y += \
hal/pmu/pmu_tu104.o \
hal/top/top_gp106.o \
hal/top/top_gp10b.o \
hal/tpc/tpc_gv11b.o
hal/tpc/tpc_gv11b.o \
hal/priv_ring/priv_ring_gv11b.o
# Linux specific parts of nvgpu.
nvgpu-y += \

3
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -391,7 +391,8 @@ endif
ifeq ($(CONFIG_NVGPU_PROFILER),1)
srcs += common/profiler/profiler.c \
common/profiler/pm_reservation.c
common/profiler/pm_reservation.c \
hal/priv_ring/priv_ring_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_KERNEL_MODE_SUBMIT),1)

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -62,6 +62,7 @@
#include "hal/class/class_gv11b.h"
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/priv_ring/priv_ring_gp10b.h"
#include "hal/priv_ring/priv_ring_gv11b.h"
#include "hal/gr/config/gr_config_gv100.h"
#include "hal/power_features/cg/gv11b_gating_reglist.h"
#ifdef CONFIG_NVGPU_COMPRESSION
@@ -1335,6 +1336,9 @@ static const struct gops_priv_ring gv11b_ops_priv_ring = {
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
.get_fbp_count = gm20b_priv_ring_get_fbp_count,
#ifdef CONFIG_NVGPU_PROFILER
.read_pri_fence = gv11b_priv_ring_read_pri_fence,
#endif
};
static const struct gops_fuse gv11b_ops_fuse = {

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -48,6 +48,7 @@
#include "hal/class/class_tu104.h"
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/priv_ring/priv_ring_gp10b.h"
#include "hal/priv_ring/priv_ring_gv11b.h"
#include "hal/power_features/cg/tu104_gating_reglist.h"
#include "hal/cbc/cbc_gm20b.h"
#include "hal/cbc/cbc_tu104.h"
@@ -1428,6 +1429,9 @@ static const struct gops_priv_ring tu104_ops_priv_ring = {
.enum_ltc = gm20b_priv_ring_enum_ltc,
.get_gpc_count = gm20b_priv_ring_get_gpc_count,
.get_fbp_count = gm20b_priv_ring_get_fbp_count,
#ifdef CONFIG_NVGPU_PROFILER
.read_pri_fence = gv11b_priv_ring_read_pri_fence,
#endif
};
#endif

4
drivers/gpu/nvgpu/hal/perf/perf_gv11b.c
View File

@@ -472,6 +472,10 @@ void gv11b_perf_reset_hwpm_pmm_registers(struct gk20a *g)
g->ops.perf.get_pmmgpc_per_chiplet_offset(),
g->num_gpc_perfmon);
}
if (g->ops.priv_ring.read_pri_fence != NULL) {
g->ops.priv_ring.read_pri_fence(g);
}
}
void gv11b_perf_init_hwpm_pmm_register(struct gk20a *g)

39
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.c Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/io.h>
#include "priv_ring_gv11b.h"
#include <nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h>
#include <nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h>
#include <nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h>
void gv11b_priv_ring_read_pri_fence(struct gk20a *g)
{
/* Read back to ensure all writes to all chiplets are complete. */
nvgpu_readl(g, pri_ringstation_sys_pri_fence_r());
nvgpu_readl(g, pri_ringstation_gpc_pri_fence_r());
nvgpu_readl(g, pri_ringstation_fbp_pri_fence_r());
}

30
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gv11b.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PRIV_RING_GV11B_H
#define NVGPU_PRIV_RING_GV11B_H
#ifdef CONFIG_NVGPU_PROFILER
struct gk20a;
void gv11b_priv_ring_read_pri_fence(struct gk20a *g);
#endif
#endif /* NVGPU_PRIV_RING_GV11B_H */

3
drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h
View File

@@ -141,6 +141,9 @@ struct gops_priv_ring {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
void (*decode_error_code)(struct gk20a *g, u32 error_code);
#ifdef CONFIG_NVGPU_PROFILER
void (*read_pri_fence)(struct gk20a *g);
#endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_NEXT)

63
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_fbp_gv11b.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef NVGPU_HW_PRI_RINGSTATION_FBP_GV11B_H
#define NVGPU_HW_PRI_RINGSTATION_FBP_GV11B_H
#include <nvgpu/types.h>
#include <nvgpu/static_analysis.h>
#define pri_ringstation_fbp_pri_fence_r() (0x001241fcU)
#endif

1
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h
View File

@@ -69,4 +69,5 @@
#define pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(r)\
(((r) >> 20U) & 0x3U)
#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU)
#define pri_ringstation_gpc_pri_fence_r() (0x001281fcU)
#endif

1
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h
View File

@@ -72,4 +72,5 @@
#define pri_ringstation_sys_priv_error_info_priv_level_v(r)\
(((r) >> 20U) & 0x3U)
#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU)
#define pri_ringstation_sys_pri_fence_r() (0x001221fcU)
#endif

63
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_fbp_tu104.h Normal file
View File

@@ -0,0 +1,63 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef NVGPU_HW_PRI_RINGSTATION_FBP_TU104_H
#define NVGPU_HW_PRI_RINGSTATION_FBP_TU104_H
#include <nvgpu/types.h>
#include <nvgpu/static_analysis.h>
#define pri_ringstation_fbp_pri_fence_r() (0x001241fcU)
#endif

3
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_gpc_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -63,4 +63,5 @@
#define pri_ringstation_gpc_gpc0_priv_error_wrdat_r() (0x00128124U)
#define pri_ringstation_gpc_gpc0_priv_error_info_r() (0x00128128U)
#define pri_ringstation_gpc_gpc0_priv_error_code_r() (0x0012812cU)
#define pri_ringstation_gpc_pri_fence_r() (0x001281fcU)
#endif

3
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_pri_ringstation_sys_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -67,4 +67,5 @@
#define pri_ringstation_sys_priv_error_wrdat_r() (0x00122124U)
#define pri_ringstation_sys_priv_error_info_r() (0x00122128U)
#define pri_ringstation_sys_priv_error_code_r() (0x0012212cU)
#define pri_ringstation_sys_pri_fence_r() (0x001221fcU)
#endif