Added GPCPLL poweron voltage field to GPU clock structure. Initialized
it differently for GPCPLL revisions B1 and C1.
Bug 1924194
Change-Id: Ide7a08445afd3ab9aea21f75871b750f45c02c99
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1481263
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Fixed below static sparse warnings by making either
function as static or including right header.
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/common/linux/module.c:816:5: warning: symbol 'gk20a_pm_init' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:28:6: warning: symbol 'gk20a_bus_init_hw' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:54:6: warning: symbol 'gk20a_bus_isr' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:90:5: warning: symbol 'gk20a_read_ptimer' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:147:6: warning: symbol 'gk20a_init_bus' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c:232:6: warning: symbol 'gk20a_init_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/fb_gk20a.c:75:6: warning: symbol 'gk20a_fb_debug_mode_enabled' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/hal_gm20b.c:184:5: warning: symbol 'gm20b_init_hal' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/fb_gm20b.c:165:5: warning: symbol 'gm20b_fb_vpr_info_fetch' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:103:5: warning: symbol 'gm20b_ltc_cbc_ctrl' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:168:6: warning: symbol 'gm20b_ltc_init_fs_state' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:195:6: warning: symbol 'gm20b_ltc_isr' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:221:5: warning: symbol 'gm20b_ltc_cbc_fix_config' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:236:6: warning: symbol 'gm20b_flush_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:350:6: warning: symbol 'gm20b_init_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/tegra/linux/clk.c:72:6: warning: symbol 'nvgpu_linux_init_clk_support' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c:206:6: warning: symbol 'gp10b_init_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/fb_gp10b.c:98:6: warning: symbol 'gp10b_init_fb' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/hal_gp10b.c:190:5: warning: symbol 'gp10b_init_hal' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c:79:6: warning: symbol 'gp10b_init_priv_ring' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp106/hal_gp106.c:222:5: warning: symbol 'gp106_init_hal' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp106/fb_gp106.c:42:6: warning: symbol 'gp106_init_fb' was not declared. Should it be static?
Bug 200299572
Change-Id: I32f9a3cb65314bd1eb1a6d93cda5796cfa64d738
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/1481804
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Introduce a priv ring HAL and define ISR as the only function in it.
Introduce a gp10b version of the ISR that writes error message to
UART for every priv ring error, and leave the old chips with silent
error handling.
Bug 1846641
Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473696
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The __nvgpu_mem_create_from_pages() API takes a number of pages from
which to create a buffer. In the ACR code only 1 page was passed. If
the WPR region (what the ACR code creates an nvgpu_mem from) is larger
than 1 page then the current code will truncate that region down to
only a single page.
Change-Id: I11833619c4f35a076f72071cc5b98ae2d192c5d0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1477672
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Begin moving (and renaming) the GMMU code into common/mm/gmmu.c. This
block of code will be responsible for handling the platform/OS
independent GMMU operations.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ide761bab75e5d84be3dcb977c4842ae4b3a7c1b3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464083
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CBC clean timeout is set to 1ms. We're seeing longer times taken
in 3dtex_deep_image, so bump the timeout significantly.
Change-Id: I16febbe663f130236c455d169c6eab47e4f73b52
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1478334
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Added function pointers to check chip specific valid
gfx class and compute class. Also added function pointer
to update ctx header with preemption buffer pointers.
Bug 200292090
Change-Id: I8119ee082e2abb67186a8ac07088f8db7f410ba1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1293502
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Clock gating list contains a register which does not exist on gm20b.
Remove it from the list.
Bug 1846641
Change-Id: Ifb6f5c46482bcaad626bc875e9858d486d3dfa1c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473223
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Use an nvgpu_mem created from a page in the ACR code instead of
a scatter gather table created by the Linux SGT APIs. The ACR code
needs to have the GPU map a physical page queried from an external
API (other than the regular DMA API).
Note that this code used to explicitly mark the SGT it makes as
bypassing the SMMU. However, that is now taken care of implicitly
by the __nvgpu_mem_create_from_pages() function.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ie40152a7611e985e1b97ac2ddc7e27664b71917c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464082
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move and rename the functions that build sgtables for nvgpu_mems into
the Linux specific DMA code.
One place outside of the Linux code do include the Linux DMA header.
That will be fixed in a subsequent patch.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ie43c752b8f998f122af70f7c7eb727af0b0d98df
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464078
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Get function declaration from fb_gm20b.h. This solves
Sparse warnings due to the missing of function prototype.
bug 200299572
Change-Id: Ie692f88e5bfc771bfcbb713adda3776521788f8c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/1468858
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Put all debugfs dependencies inside #ifdef CONFIG_DEBUG_FS. This
includes some functions in allocators that were used only for
debugging.
Remove include of linux/debugfs.h on files that do not deal with
debugfs.
linux/debugfs.h implicitly included linux/fs.h, which we relied on.
Add explicit include of linux/fs.h for all files where this is the
case.
Change-Id: I16feffae6b0e3a2edf366075cdc01ade86be06f9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1467897
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Hide the Linux specific nvgpu_mem fields so that in subsequent patches
core code can instead of using struct sg_table it can use mem_desc.
Routines for accessing system specific fields will be added as needed.
This is the first step in a fairly major overhaul of the GMMU mapping
routines. There are numerous issues with the current design (or lack
there of): massively coupled code, system dependencies, disorganization,
etc.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I2e7d3ae3a07468cfc17c1c642d28ed1b0952474d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464076
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Separated parameters for GM20B GPC PLL revisions B1 (default), and C1
(new, not characterized, yet). For now, used C1 spec settings.
Skipped PL divider glitch WAR, since revision C1 is glitchless.
Bug 1851797
Bug 1867980
Change-Id: I12dc101d002a41230e9323c47af234f6bae8e034
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1461680
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Copy is_fmodel to struct gk20a at probe time, and access it from
gk20a instead of platform_gk20a.
JIRA NVGPU-16
Change-Id: Ib8d793ea2b02b62da3bfdbb6372d9927658b7ec6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463540
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add nvgpu_firmware data structure, and return it instead of Linux
struct firmare from nvgpu_request_firmware. Also add abstraction
for releasing firmware: nvgpu_release_firmware.
JIRA NVGPU-16
Change-Id: I6dae8262957c0d4506f710289e3a43a6c1729fc7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463538
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Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I05df9d72edaf4bb061febe0cb40fc8a7cf9f51c7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460114
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I46b9ccb80e0b67efb86ec85676e5a55ff835c0ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Add nvgpu_* wrappers for determining if we're running in simulation
or silicon, and if we're running in hypervisor.
The new wrappers require struct gk20a pointer, and gk20a_fence_wait()
did not have access to one. Add struct gk20a pointer as the first
parameter.
JIRA NVGPU-16
Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1331565
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gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.
JIRA NVGPU-16
Change-Id: Ic27fb98e03a982e5a1cf672cb4e8f87ecea10a5b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1457345
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Rename the nvgpu DMA APIs from gk20a_gmmu_alloc* to nvgpu_dma_alloc*.
This better reflects the purpose of the APIs (to allocate DMA suitable
memory) and avoids confusion with GMMU related code.
JIRA NVGPU-12
Change-Id: I673d607db56dd6e44f02008dc7b5293209ef67bf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1325548
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Make an nvgpu DMA API include file so that the intricacies of the
Linux DMA API can be hidden from the calling code.
Also document the nvgpu DMA API.
JIRA NVGPU-12
Change-Id: I7578e4c726ad46344b7921179d95861858e9a27e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1323326
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Renaming was done with the following command:
$ find -type f | \
xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g'
Also rename mem_desc.[ch] to nvgpu_mem.[ch].
JIRA NVGPU-12
Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1325547
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Add wrapper header nvgpu/types.h. It checks if build is for Linux
kernel and pulls in linux/types.h.
Delete also all #includes for linux/types.h which are not strictly
necessary, and change the remaining ones to use the new wrapper.
JIRA NVGPU-13
Change-Id: I1ddfef0b0b9d840e3e41a62f69c7cb9148d2d5fa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1453371
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Use the new kmem API functions in gk20a's mm code. Add a struct
gk20a pointer to the dmabuf priv struct so that the cleanup
function has access to the gk20a struct. Also add a gk20a pointer
to some of the sg table functions so that they can use the nvgpu
kmem APIs.
Bug 1799159
Bug 1823380
Change-Id: I85a307c6bf862627c5b1af0e077283b48d78fa72
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1318321
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
ctrl_gk20a.c had some direct accesses to hardware. These violate the
HAL rules, because we don't have per-GPU ctrl, and thus the code
cannot be made GPU independent.
Move all GR accesses to new GR HALs and use existing bus HAL for
accessing timer. Remove #includes of all hardware headers.
JIRA NVGPU-28
Change-Id: I57e67519f62e9bd6c3e725e1bef6e366190f5834
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1327001
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Move code that touches host registers and instance block to fifo HAL.
This involves adding HAL ops for the fifo HAL functions that get
called from outside fifo. This clears responsibility of channel by
leaving it only managing channels in software and push buffers.
channel had member ramfc defined, but it was not used, to remove it.
pbdma_acquire_val consisted both of channel logic and hardware
programming. The channel logic was moved to the caller and only
hardware programming was moved.
Change-Id: Id005787f6cc91276b767e8e86325caf966913de9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1322423
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Move the name field from struct gpu_ops up to struct gk20a. The field
is not a function op, so it doesn't belong in gpu_ops.
Replace all uses of dev_name() with use of g->name when possible.
JIRA NVGPU-16
Change-Id: Ic6e99e39258cbf3bb7c806962cbbd7de5126688f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1328534
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fifo reset_enable_hw is reorged to clear and enable pbdma/fifo interrupts
after all the required configuration such as configuring timeouts,
enabling timeout detections are taken care of.
JIRA GPUT19X-74
JIRA GPUT19X-47
Change-Id: Id780cc11d858db18f8d748c037954ede73298506
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325351
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Use the new kmem API functions in gm20b/*. Also add a struct gk20a
pointer to
lsfm_free_ucode_img_res()
lsfm_free_nonpmu_ucode_img_res()
so nvgpu_kfree() works.
Bug 1799159
Bug 1823380
Change-Id: I3373600455553710adb14e0fb5743bf197095a03
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1318320
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Clean up gk20a.c by removing direct accesses to MC and moving the
accesses to happen via MC HAL.
The chip detection logic has to violate the HAL and call gk20a
version directly, because HAL ops cannot be set up before chip has
been identified.
Change-Id: I4cdd0ef3fcf7d3b561a3fca4247a8356fe8d18e1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1321576
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After driver remove, the device structure passed in gk20a_busy can be
invalid. To solve this the prototype of the function is modified to pass
the gk20a struct instead of the device pointer.
bug 200277762
JIRA: EVLR-1023
Change-Id: I08eb74bd3578834d45115098ed9936ebbb436fdf
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1320194
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks for each GPU version separately
pbdma_intr_0 field differences for each GPU version:-
-gk20a : bit 28 does not exists in hw
-gm20b : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw
-gp10b : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28,
(syncpoint_illegal) added in hw but is not being handled.
-gk20a/gm20b/gp10b
bit 24 eng_reset and bit 25 semaphore always existed in hw but never
handled
JIRA GPUT19X-47
Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325402
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Don't use enum dma_attr in the gk20a_gmmu_alloc_attr* functions, but
define nvgpu-internal flags for no kernel mapping, force contiguous, and
read only modes. Store the flags in the allocated struct mem_desc and
only use gk20a_gmmu_free, remove gk20a_gmmu_free_attr. This helps in OS
abstraction. Rename the notion of attr to flags.
Add implicit NVGPU_DMA_NO_KERNEL_MAPPING to all vidmem buffers
allocated via gk20a_gmmu_alloc_vid for consistency.
Fix a bug in gk20a_gmmu_alloc_map_attr that dropped the attr
parameter accidentally.
Bug 1853519
Change-Id: I1ff67dff9fc425457ae445ce4976a780eb4dcc9f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1321101
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
