Commit Graph

2291 Commits

Author SHA1 Message Date
Peter Daifuku
42db3e1879 gpu: nvgpu: vgpu: profiler reservation support
Support for hwpm reservations in the virtual case:

- Add session ops for checking and setting global and context reservations, and
  releasing reservations
- in the native case, these just update reservation counts and flags
- in the vgpu case, when the reservation count is 0, check with the RM server
  that a reservation is possible: for global reservations, no other guest
  can have a reservation; for context reservations, no other guest can have
  a global reservation
- in the vgpu case, when the reservation count is decremented to 0, notify
  the RM server that the guest no longer has any reservations

Bug 1775465
JIRA VFND-3428

Change-Id: Idf115b730e465e35d0745c96a8f8ab6b645c7cae
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1326166
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-24 19:36:08 -07:00
David Nieto
2fce77c286 gpu: nvgpu: Add refcounting to driver fds
The main driver structure is not refcounted properly,
so when the driver unload, file desciptors associated to the
driver are kept open with dangling references to the main object.

This change adds referencing to the gk20a structure.

bug 200277762
JIRA: EVLR-1023

Change-Id: Id892e9e1677a344789e99bf649088c076f0bf8de
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1317420
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 74fe1caa2b)
Reviewed-on: http://git-master/r/1324637
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
2017-03-24 08:24:11 -07:00
David Nieto
26f904e2b7 gpu: nvgpu: fix arbiter teardown on PCI
The driver is not properly tearing down the arbiter on the PCI driver
unload. This change makes sure that the workqueues are drained before
tearing down the driver

bug 200277762
JIRA: EVLR-1023

Change-Id: If98fd00e27949ba1569dd26e2af02b75897231a7
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1320147
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit 469308beca)
Reviewed-on: http://git-master/r/1324636
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
2017-03-24 08:24:10 -07:00
Deepak Nibade
ce057d784d gpu: nvgpu: take power refcount in gk20a_cde_convert()
We have a gk20a_busy() call in gk20a_buffer_convert_gpu_to_cde()
and we again call gk20a_busy() in gk20a_submit_channel_gpfifo()

If gk20a_do_idle() is triggered in between these two calls,
then this leads to a deadlock and results in idle failure

Hence to avoid this take power refcount in a more fine-grained
way i.e. in gk20a_cde_convert() instead of taking in
gk20a_buffer_convert_gpu_to_cde()

Keep gk20a_cde_execute_buffer() out of the gk20a_busy()/
gk20a_idle() pair since we take power refcount in submit path
anyways

Add correct error handling path in gk20a_cde_convert()

Bug 200287073

Change-Id: Iffea2d4c03f42b47dbf05e7fe8fe2994f9c6b37c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1324329
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2017-03-21 15:27:09 -07:00
Deepak Nibade
3c8eef0d0e gpu: nvgpu: hold mutex to get cde context only
In gk20a_cde_convert(), we hold cde_app.mutex almost
for everything which is unnecessary

Also, this causes a deadlock scenario when gk20a_do_idle()
is called
In some cases it is possible that Thread 1
holds the lock and is trying to power on GPU, and
Thread 2 is trying to power off GPU and then grab
cde_app.mutex to cleanup GPU state

To fix this, grab the mutex only for gk20a_cde_get_context()
and then release it

Bug 200287073

Change-Id: Ic4856604652d0d4024abdeb5c2f8f03910c601a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1324328
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2017-03-21 15:27:08 -07:00
Peter Daifuku
009d9fd7f7 gpu: nvgpu: profiler create/free, hwpm reserve
Add support for creating/freeing profiler objects, hwpm reservations

Bug 1775465
JIRA EVLR-680
JIRA EVLR-682

Change-Id: I4db83d00e4b0b552b05b9aae96dc553dd1257d88
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1322487
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-20 06:42:26 -07:00
Rajkumar Kasirajan
22ac82a075 Revert "gpu: nvgpu: change stall intr handling order"
This reverts commit 35f0cf0efe as
it caused lp0 suspend/resume failure.

Bug 1886110

Change-Id: Ib62207650344180361b6529f716f77b84528cd56
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-on: http://git-master/r/1317986
(cherry picked from commit e4a131a98d)
Reviewed-on: http://git-master/r/1320905
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-20 06:42:12 -07:00
David Nieto
fe2b83ef4d gpu: nvgpu: refactor interrupt handling
JIRA: EVLR-1004

(*) Refactor the non-stalling interrupt path to execute clear on the
top half, so on dGPU case processing of stalling interrupts does not
block non-stalling one.
(*) Use a worker thread to do semaphore wakeups and allow batching of
the non-stalling operations.
(*) Fix a bug where some gpus will not properly track the completion
of interrupts, preventing safe driver unloads

Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1312796
Reviewed-on: http://git-master/r/1320848
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
2017-03-20 06:42:07 -07:00
Sachit Kadle
57dafc08a5 gpu: nvgpu: vgpu: add freq capping support
Currently callbacks from the PM_QOS framework (for
thermal events), result in a RPC call to set GPU frequency.

Since the governor will now be responsible for setting desired
rate, the max PM_QOS callback will now cap the possible
GPU frequency w/ a new RPC call to the server. The server
is responsible for setting the ultimate frequency
based on the cap & desired rates.

Jira VFND-3699

Change-Id: I806e309c40abc2f1381b6a23f2d898cfe26f9794
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1295543
(cherry picked from commit e81693c6e087f8f10a985be83715042fc590d6db)
Reviewed-on: http://git-master/r/1282467
(cherry picked from commit 7b4e0db647572e82a8d53e823c36b465781f4942)
Reviewed-on: http://git-master/r/1321836
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-03-20 03:13:53 -07:00
Sachit Kadle
f871b52fd3 gpu: nvgpu: vgpu: add devfreq support
Add devfreq governor support in order to allow frequency scaling
in virtualization config. GPU clock frequency operations are
re-directed to the server over RPC.

Bug 200237433

Change-Id: I1c8e565a4fff36d3456dc72ebb20795b7822650e
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1295542
(cherry picked from commit d5c956fc06697eda3829c67cb22987e538213b29)
Reviewed-on: http://git-master/r/1280968
(cherry picked from commit 25e2b3cf7cb5559a6849c0024d42c157564a9be2)
Reviewed-on: http://git-master/r/1321835
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-03-20 03:13:48 -07:00
Peter Daifuku
0eb5255e54 gpu: nvgpu: del channel job before fence is closed
In gk20a_channel_clean_up_jobs, move removal of job from channel's job list
to before fences are cleaned up; this will prevent gk20a_channel_abort from
asynchronously trying to dereference an already freed job.

Bug 1844305
JIRA EVLR-849

Change-Id: I1ba05237aa74be1350007630bfa5eba9988f859a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
(cherry picked from commit 2a9ce58b1b318b95ecfcdf78462f918d090eab99)
Reviewed-on: http://git-master/r/1319026
(cherry picked from commit 990f070b0a363159ce1b21f936b7512f469018ca)
Reviewed-on: http://git-master/r/1322332
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-18 07:11:23 -07:00
Aparna Das
b6a2aa3631 gpu: nvgpu: vgpu: force gpu preepmtion policy
Query the RM server to retrieve gpu preemption policy
of guest based on pct configuration. If guest is not
allowed to request wfi preemption mode then set context
with either gfxp or cta preemption mode only.

Jira VFND-3079
Jira VFND-3081

Change-Id: I60cbf121d6f0e2373568cf40b3dfdb4df76fe02d
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: http://git-master/r/1280903
(cherry picked from commit 16ee09bb59)
Reviewed-on: http://git-master/r/1321661
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-18 07:11:11 -07:00
Seema Khowala
4deb494ad1 gpu: nvgpu: debug dump enablement for t19x
Fifo ops added for dumping channel & ramfc status
and pbdma & engine status.


Change-Id: Icc739f4f05f0864721954489517fefdfa2fa608a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1302369
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-09 12:23:29 -08:00
Thomas Fleury
2caea7576a gpu: nvgpu: vgpu: add clear single SM error state
Add support for clearing single SM error state for CUDA debugger.
In addition to clearing local copy of SM error state,
vgpu_gr_clear_sm_error_state now sends a command to RM server
(TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE), to clear global ESR and
warp ESR.

Bug 1791111

Change-Id: I3a1f0644787fd900ec59a0e7974037d46a603487
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1296311
(cherry picked from commit fd07e03c3d086f396e4d65575c576a4dd68c920a)
Reviewed-on: http://git-master/r/1299060
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Tested-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-09 10:44:56 -08:00
Thomas Fleury
6c35cebdcb gpu: nvgpu: vgpu: suspend/resume contexts
Add ability to suspend/resume contexts for a debug session
(NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS), in virtualized
case:
- added hal function to resume contexts.
- added vgpu support for suspend contexts, i.e. build a list
of channel ids, and send TEGRA_VGPU_CMD_SUSPEND_CONTEXTS
- added vgpu support for resume contexts, i.e. build a list
of channel ids, and send TEGRA_VGPU_CMD_RESUME_CONTEXTS

Bug 1791111

Change-Id: Icc1c00d94a94dab6384ac263fb811c00fa4b07bf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1294761
(cherry picked from commit d17a38eda312ffa92ce92e5bafc30727a8b76c4e)
Reviewed-on: http://git-master/r/1299059
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Cory Perry <cperry@nvidia.com>
Tested-by: Cory Perry <cperry@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-09 10:44:55 -08:00
Richard Zhao
bc47d82229 gpu: nvgpu: add NVGPU_GPU_FLAGS_SUPPORT_MAP_COMPBITS
native gpu driver supports map compbits but vgpu does not.

Bug 1778448
Bug 200275051
JIRA VFND-3513

Change-Id: I433a6f8631b495875ba899af9609203ab36187ef
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1314065
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-08 11:35:24 -08:00
Richard Zhao
baf464779e gpu: nvgpu: vgpu: remove cycle stats from characteristics
vgpu does not support cycle stats.

Bug 1781434
Bug 200275051
JIRA VFND-3513

Change-Id: Id1d566027913632fc8a4f0285609be5f56b26288
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1314064
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-08 09:55:43 -08:00
David Nieto
b9feba6efc gpu: nvgpu: in-kernel kickoff profiling
Add a debugfs interface to profile the kickoff ioctl
it provides the probability distribution and separates the information
between time spent in: the full ioctl, the kickoff function, the amount
of time spent in job tracking and the amount of time doing pushbuffer
copies

JIRA: EVLR-1003

Change-Id: I9888b114c3fbced61b1cf134c79f7a8afce15f56
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1308997
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-07 13:42:28 -08:00
Konsta Holtta
b9991767cc gpu: nvgpu: drop 0x in front of timed out symbol
The Linux timer code prints an error message containing the caller when
a timeout happens. The caller is formatted as a function name instead of
a pointer, so don't print 0x in front of it.

Bug 1799159

Change-Id: I4f86d885aba78ca20ba025a91c8c940d3c927d58
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1315749
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-07 08:09:37 -08:00
Seema Khowala
3b0e010d14 gpu: nvgpu: add fifo ops for *client_type_gpc_v
*client_type_gpc_v is different for t19x

Change-Id: Ic8f8eff2d98138a877ef95c6f7f40226f0d61a61
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313436
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-03-07 02:35:01 -08:00
Vijayakumar
b0973391d0 gpu: nvgpu: add pmu trace support for dgpus
1) Trace buffer allocation now calls generic gmmu alloc/map.
  so for dGPUs they are allocated in vidmem and iGPUs they
are allocated in sysmem

2) Use pmu surface mechanism to setup trace buffer params as
dGPU binaries follow falcon memory structure to get mem surface
params

3) Fix minor coverity issue by removing unnecessary overwrite
of count variable in trace print function

JIRA DNVGPU-217

Coverity ID 2431386

Change-Id: I2ae49a4e0450481cde2a778447c270a796681dad
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1312404
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-03-07 00:10:50 -08:00
Seema Khowala
35f0cf0efe gpu: nvgpu: change stall intr handling order
-Handle pbus and priv stall interrupts first.
 In general critical interrupts should be
 handled before any other non critical ones.

-Dump info enabled with gpu_dbg_intr if priv_ring
 interrupt is flagged by fmodel.

JIRA NVGPU-25

Change-Id: Iee767d8c9c933ceb57532c1b5a7fd7812daf1b6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1311273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-07 00:10:44 -08:00
Terje Bergstrom
d6ff5ef649 gpu: nvgpu: Disable trace_printk use by default
trace_printk() does an extra stringify operation before calling
do_trace_printk(). The string ends up unused. This has an impact
to kernel even if we never end up using trace_printk().

Disable use of trace_printk() and introduce a Kconfig option for
re-enabling it.

Change-Id: I2e1014f5231f2089d7dc3cb2539e3eb5f4d58361
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1295298
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-03-07 00:10:41 -08:00
Alex Waterman
707ea45e0f gpu: nvgpu: kmem abstraction and tracking
Implement kmem abstraction and tracking in nvgpu. The abstraction
helps move nvgpu's core code away from being Linux dependent and
allows kmem allocation tracking to be done for Linux and any other
OS supported by nvgpu.

Bug 1799159
Bug 1823380

Change-Id: Ieaae4ca1bbd1d4db4a1546616ab8b9fc53a4079d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283828
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-03 10:34:48 -08:00
Alex Waterman
3966efc2e5 gpu: nvgpu: Give nvgpu_kalloc a less generic name
Change nvgpu_kalloc() to nvgpu_big_[mz]alloc(). This is necessary
since the natural free function name for this is nvgpu_kfree() but
that conflicts with nvgpu_k[mz]alloc() (implemented in a subsequent
patch).

This API exists becasue not all allocation sizes can be determined
at compile time and in some cases sizes may vary across the system
page size. Thus always using kmalloc() could lead to OOM errors due
to fragmentation. But always using vmalloc() is wastful of memory
for small allocations. This API tries to alleviate those problems.

Bug 1799159
Bug 1823380

Change-Id: I49ec5292ce13bcdecf112afbb4a0cfffeeb5ecfc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1283827
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-03-03 10:34:43 -08:00
Alex Waterman
76b78b6fdc gpu: nvgpu: Remove nvgpu_gpuid_t18x.h
Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate
the relevant definitions and defines into their expected places and
make the code use the real defines. No longer is hiding t18x specific
stuff necessary.

Bug 1799159

Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1300976
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-02 18:48:41 -08:00
vishnu Reddy
f9b2c30b36 gpu: nvgpu: Add and move FECS trace flag
Added fecs trace characteristic flag to vgpu to determine for
platform support

Also moved fecs flag from ctxsw init to fecs init for native linux.
This makes flag init uniform across both platforms.

JIRA EVLR-993

Change-Id: Id62f31954cb5d7028ef01a199548f5f908b51eb0
Signed-off-by: Vishnu Reddy Mandalapu <vmandalapu@nvidia.com>
Reviewed-on: http://git-master/r/1305045
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2017-03-02 18:15:47 -08:00
Konsta Holtta
f1072a28be gpu: nvgpu: add worker for watchdog and job cleanup
Implement a worker thread to replace the delayed works in channel
watchdog and job cleanups. Watchdog runs by polling the channel states
periodically, and job cleanup is performed on channels that are appended
on a work queue consumed by the worker thread. Handling both of these
two in the same thread makes it impossible for them to cause a deadlock,
as has previously happened.

The watchdog takes references to channels during checking and possibly
recovering channels. Jobs in the cleanup queue have an additional
reference taken which is released after the channel is processed. The
worker is woken up from periodic sleep when channels are added to the
queue.

Currently, the queue is only used for job cleanups, but it is extendable
for other per-channel works too. The worker can also process other
periodic actions dependent on channels.

Neither the semantics of timeout handling or of job cleanups are yet
significantly changed - this patch only serializes them into one
background thread.

Each job that needs cleanup is tracked and holds a reference to its
channel and a power reference, and timeouts can only be processed on
channels that are tracked, so the thread will always be idle if the
system is going to be suspended, so there is currently no need to
explicitly suspend or stop it.

Bug 1848834
Bug 1851689
Bug 1814773
Bug 200270332
Jira NVGPU-21

Change-Id: I355101802f50841ea9bd8042a017f91c931d2dc7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1297183
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-02 17:51:03 -08:00
Seema Khowala
0c155313e7 gpu: nvgpu: use litter val for pbdma/eng *status__size*
fifo_pbdma_status__size_1_v() and fifo_engine_status__size_1_v()
are not same for all gpus. Use litter value to calculate chip
specific fifo*status__size_1(v)

JIRA GV11B-45

Change-Id: I3d3d45bf79d15e14739fcc18cb1ca987669d5c11
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1312688
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 15:05:28 -08:00
Sandeep Shinde
ee93b20963 gpu: nvgpu: Allow compute preemption mode on PASCAL_A class
Remove restriction of setting compute preemption mode for channels
created with PASCAL_COMPUTE_A class only and allow it to be set
for PASCAL_A class too.

Also print compute preemption mode during channel closing.

Bug 200284575

Change-Id: I2de3b3acda128e91caa2ab0fd341915ce6e6520b
Signed-off-by: Sandeep Shinde <sashinde@nvidia.com>
Reviewed-on: http://git-master/r/1313286
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Donghan Ryu <dryu@nvidia.com>
2017-03-02 11:44:47 -08:00
Terje Bergstrom
b71fa9289d gpu: nvgpu: Do not bind FECS trace on VPR channels
VPR channels can access VPR, and writing to FECS buffer outside of
VPR causes a region violation.

Bug 1877511

Change-Id: Ida466c81e928d1f67bf1b0e7dd6afb799c1ab2f6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1312759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Tested-by: Season Li <seasonl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
2017-03-02 10:43:40 -08:00
seshendra Gadagottu
f8ec82237e gpu: nvgpu: check for pmu enable
Check for pmu enable, before calling pmu_destrory().

Change-Id: I64c5071ed69b6b50140e46da48a2b165c1f7ba02
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1313391
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 10:14:30 -08:00
Seema Khowala
3c3f947cf4 gpu: nvgpu: add fifo ops for *data_fault_id_enum_v
generated hw header for top_device_info_data_fault_id_enum_v
is different between legacy chips and t19x

JIRA GV11B-7

Change-Id: I877e88a5b1b1f3f41bc72b895536f4a01b4fbd4e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-03-02 08:53:38 -08:00
Seema Khowala
0aafa9e279 gpu: nvgpu: gm20b: add gr ops for load tpc mask
gr_fe_tpc_fs_r addr is different for t19x

Change-Id: I9868fcaf94d063753c4ecf1970b53374cb67b380
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1310326
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 08:53:32 -08:00
Deepak Nibade
64e1782aee gpu: nvgpu: optimize duplicate buffer lookup in case of fixed offsets
In gk20a_vm_map_duplicate_locked(), we always do a linear search
in rb-tree to find a duplicate entry of the buffer

In case NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET is set, we first
traverse whole rb-tree linearly and then compare offset_align
with the address searched from rb-tree

If size of rb-tree is very large this linear lookup takes upto
7mS and causes huge delays

Hence in case of NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET, we can
use offset_align to perform a binary search on rb-tree and then
verify that dmabuf and kind match with the node obtained from
the search
This saves a lot of time per-lookup

Bug 1874516

Change-Id: Ia4924b64d66e586c14341ae2e2283beac394bf6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1309343
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-03-02 07:53:55 -08:00
Thomas Fleury
09504cdbc3 gpu: nvgpu: remove clock domain aliases
Remove MCLK and GPCCLK domain aliases, now that userspace
has swithed to new enumerations.

Jira DNVGPU-211

Change-Id: I2af2fd67dbed47088d7161ba0605e13dd7c674a5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1292609
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
2017-03-02 02:03:35 -08:00
Seema Khowala
0a3e5941ff gpu: nvgpu: add pbdma and eng bitmask for runlists
-Init pbdma and engine bit mask per runlist.
-Organize debug info to print supported pbdma instances
 for particular runlist.

JIRA GV11B-3

Change-Id: Ie34dd98ccbe2c779ca1c795855c2a7df4abd2715
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1309706
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-27 10:13:22 -08:00
Thomas Fleury
ac8cea9351 gpu: nvgpu: ignore set preempt mode to default
In native case, attempting to set graphics/compute preempt mode
to default is ignored if preemption mode has already been set
for the context. In virtualized case an error is currently
returned.
Align behaviour for native and virtualized case, by ignoring
such request.

Bug 200186530

Change-Id: Ieb3a37107bdbd3284804ee9fd392786409224082
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1306506
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-02-24 12:14:17 -08:00
Deepak Goyal
45303a7de5 gpu: nvgpu: pmu: make gp106_pmu_reset() public.
secure PMU reset i.e. gp106_pmu_reset() is changed
to a non-static function, so that it can be re-used
outside gp106 scope.

Change-Id: I7d4c4ec6ca1bd315bf8c681723fb350277103c3b
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-02-23 21:33:34 -08:00
Deepak Goyal
d6e40fc07a nvgpu: gpu: pmu: Use pmu ops to call pmu_reset().
In this patch hard coded function calls for PMU
reset are replaced by PMU ops.

Change-Id: I266c43e3540163a133895244dcf91169116812f5
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303757
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-23 21:33:33 -08:00
Mahantesh Kumbar
9c68af58a9 gpu: nvgpu: ACR interface headers reorganization
-Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to
Its specific header files under “drivers/gpu/nvgpu/include/nvgpu/acr/”
Folder.

- nvgpu_acr.h - Top-level header-file which include ACR interfaces
headers & defines required to communicate with ACR, including this
header file is good to get access into ACR interface & made changes
accordingly,

-Deleted acr.h & acr_t18x.h as not required anymore
& removed its include from dependent files.

Jira NVGPU-19

Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304748
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-23 01:04:48 -08:00
Deepak Nibade
8cdb91c527 gpu: nvgpu: remove use of DEFINE_MUTEX()
API DEFINE_MUTEX() is defined in Linux and might
not be available in other OSs.
Hence remove its usage from nvgpu

Declare and explicitly initialize below mutexes
for both nvgpu and vgpu
g->mm.priv_lock
g->mm.tlb_lock

Jira NVGPU-13

Change-Id: If72885a6da0227a1552303206172f1f2b751471d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1298042
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-22 04:15:08 -08:00
Deepak Nibade
8ee3aa4b31 gpu: nvgpu: use common nvgpu mutex/spinlock APIs
Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>

Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()

And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>

Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h

Jira NVGPU-13

Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-22 04:15:02 -08:00
Deepak Nibade
1f855af63f gpu: nvgpu: add mutex and spinlock abstraction files
Add new abstraction file <nvgpu/lock.h> for all mutex,
spinlock and raw_spinlock operations.

Add linux specific file <nvgpu/lock_linux.h>
which implements linux specific operations for above

Jira NVGPU-13

Change-Id: Idab96aa8bf949d6a92ea0edc9f40e90fca401ea4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293186
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2017-02-22 04:14:57 -08:00
Deepak Nibade
76611c4268 gpu: nvgpu: remove use of mutex_is_locked()
mutex_is_locked() API is defined on Linux only
and not on other OS like QNX.

Hence remove use of this API for OS abstraction
support to nvgpu.

Instead of using mutex_is_locked(), use
mutex_trylock() for same purpose

Jira NVGPU-13

Change-Id: I542daf20a2294153da8e8bfe89e0dc0387297523
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1297184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-22 04:14:57 -08:00
Alex Waterman
e99a3dec3a gpu: nvgpu: Disable IRQs only if enabled
In the PCI init/de-init code only disable IRQs if they were enabled.
The enable happens in the common power_on code. The PCI routines could
both be called without the common power_on code being called which
causes an extra disable to happen.

Bug 200275531

Change-Id: I43a8a9881f1e9ae254bf36230f29849df074657f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1301701
(cherry picked from commit cca70e9adccee1ef65a0a6d95a4494fc87500c17)
Reviewed-on: http://git-master/r/1298954
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-02-21 20:42:49 -08:00
Konsta Holtta
00ba4c0b0b gpu: nvgpu: assign ce_ctx->vm during ctx creation
Commit 7e403974d3 ("gpu: nvgpu: Simplify
ref-counting on VMs") accidentally broke the CE context creation while
moving away from direct ch->vm assignments. ce_ctx->vm isn't part of
that simplification, so initialize it because it's used elsewhere and
were left NULL.

Bug 1846718

Change-Id: I6219880227b881d2175005b7eaf6e6e08a6f888e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1306221
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-02-21 11:13:42 -08:00
Terje Bergstrom
c218fefe84 gpu: nvgpu: Fix unicast register accesses for SM
In two places we used broadcast register as base, but added the
unicast offset to it. This causes the write to go well beyond
valid register range.

Change the broadcast base to use unicast base instead in sequence
to resume a single SM and to record error state of SM.

Bug 200256272

Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c)
Reviewed-on: http://git-master/r/1306331
Reviewed-by: Automatic_Commit_Validation_User
2017-02-17 15:30:58 -08:00
Terje Bergstrom
4b8edeffe5 gpu: nvgpu: Prune gp106 clock gating list
Further prune registers that do not exist on gp106 that were not
caught by previous patch.

Bug 200256272

Change-Id: Ic8d6835d8726d850860d680dd1807e8020010a29
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit c1c9029b9b851652d7b62a96373d7c1636f3ad89)
Reviewed-on: http://git-master/r/1306330
Reviewed-by: Automatic_Commit_Validation_User
2017-02-17 15:30:58 -08:00
Terje Bergstrom
6a58857b65 gpu: nvgpu: Remove almost all gm204/gm206 support
Remove gm204/gm206 support. It was used only in the interim until
Pascal cards were available, and we don't maintain that code anymore.

This patch leaves only BIOS code.

Change-Id: I215988603d4588ef710bdda6e47449e9235e78ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302224
GVS: Gerrit_Virtual_Submit
2017-02-17 13:46:32 -08:00