nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 18:16:01 +03:00
Code Issues Packages Projects Releases Wiki Activity
4,968 Commits 57 Branches 84 Tags
4e6d9afab87fce6b0a5c18b51d174ec7f800b19c
Commit Graph

103 Commits

Author SHA1 Message Date
Seshendra Gadagottu
df6d5ab07b gpu: nvgpu: gp10b: Add Bar2 support 
Add bar2 support for gp10b and set-up bar2 binding.

Bug 1587825

Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/659236
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
945e5e6832 gpu: nvgpu: gp10b: Correct SMMU bit number 
Bit 36 is the correct bit to indicate SMMU translation.

Bug 1580756

Change-Id: I761e70265d5981b07940f1d43716416829993827
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/658827
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
c23f7708ac gpu: nvgpu: gp10b: Define physical address width 
GP10B physical address width is 37 bits. Use old width for now,
and add gp10b specific definition. We can switch to new definition
once we've verified them.

Bug 1567274

Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601703
 2016-12-27 15:22:02 +05:30