Add gk20a_channel_from_id() to retrieve a channel, given a raw channel
ID, with a reference taken (or NULL if the channel was dead). This makes
it harder to mistakenly use a channel that's dead and thus uncovers bugs
sooner. Convert code to use the new lookup when applicable; work remains
to convert complex uses where a ref should have been taken but hasn't.
The channel ID is also validated against FIFO_INVAL_CHANNEL_ID; NULL is
returned for such IDs. This is often useful and does not hurt when
unnecessary.
However, this does not prevent the case where a channel would be closed
and reopened again when someone would hold a stale channel number. In
all such conditions the caller should hold a reference already.
The only conditions where a channel can be safely looked up by an id and
used without taking a ref are when initializing or deinitializing the
list of channels.
Jira NVGPU-1460
Change-Id: I0a30968d17c1e0784d315a676bbe69c03a73481c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955400
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the result of a bitwise operation is used as
boolean in the controlling expression of if and loop statements.
Changed few enums into macros because they were used in bit-shift &
bitwise operations and MISRA rule 10.1 forbids the usage of signed
types in bit-shift & bitwise operations.
JIRA NVGPU-1020
Change-Id: Ibc81c1e951342a5faf422ea73d13ef583535b768
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
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Don't enable GK20A by default as it does not compile against upstream
kernel.
GK20A is anyway selected explicitly as =m in most of our defconfig
files so this change has little or no effect in current builds.
Bug 2449517
Change-Id: I51e8647d78cd2118d8aa515d614e405b97e0ee6e
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1957705
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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changes in path because we move the nvhost linux user-interface
from include/linux/ to include/uapi/linux
depends on I2e116dc8f6c33f53c03fb56b923931b6e600b534
Bug 2062672
Change-Id: If2e165852432d5795cf6680cfeb5d4b661fdee74
Signed-off-by: Anuj Gangwar <anujg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1953731
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions. Also set pointer to NULL when freed.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I21ff1ae93ac7b92a71502f97785252c04964e72f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954003
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For a given channel, userd_iova is computed as an offset from
fifo->userd address. If nvlink is enabled we need fifo->userd
buffer to be physically contiguous, as nvlink bypasses IOMMU.
Otherwise, it may result in loading PBDMA from an invalid
location in memory. This manifests most of the time with either
channel timeout (GP_PUT loaded with 0, hence no progress) or
GPPTR Invalid Error (GP_PUT loaded with out of range index).
Use NVGPU_DMA_FORCE_CONTIGUOUS for fifo->userd buffer, when
nvlink is enabled.
Bug 2422486
Change-Id: I99d585ee196534025522a1cbd74fb4e4c03df98e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954802
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs to
qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches over non-offending memcpy() uses in gr/pmu/volt
code to nvgpu_memcpy() with appropriate casts applied to maintain
consistency within the nvgpu source base.
Also fixed a Rule 8.3 violation in vfe_var.c by sync'ing the param
names between declarations of the devinit_get_vfe_var_table()
routine.
JIRA NVGPU-849
Change-Id: I004b461988bd3a26212b6fbf660ee7fa742ea1ba
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1952984
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The BIOS_GET_FIELD() macro does a simple bit mask and shift operation.
The value of this macro is assigned to variables of different data
types. Casting the macro to different data types causes MISRA rule
10.8 violations. This issue is resolved by doing the cast inside the
macro and returning the value in the correct data type. These changes
also clear MISRA rule 10.1, 10.3 and 10.4 violations.
JIRA NVGPU-992
JIRA NVGPU-1006
JIRA NVGPU-1010
Change-Id: I16345865d107f0ff0b34daa8b17d7d576eafcfbf
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936357
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The return type of the function pointer *calc_global_ctx_buffer_size()
is changed from int to u32 and all its implementations.
The arg type of size in *set_big_page_size() is changed from int to
u32 and all it implementations. These changes are necessary because
size should be an unsigned value.
JIRA NVGPU-992
Change-Id: I3e4cd1d83749777aa8588a44a48772e26f190c4d
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950503
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Simplify object ownership by passing the gr_ctx around directly instead
of reading from tsg via a channel; the caller holds the gr_ctx already.
Also pass the channel vm and vpr flag instead of the whole channel as
only those are needed.
Jira NVGPU-1149
Change-Id: Ic0921ccaf65f208105b25f08f8d7b581a56b40fe
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925431
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Simplify object ownership by passing the gr_ctx around directly instead
of reading from tsg via a channel; the caller holds the gr_ctx already.
Also pass the channel vm instead of the whole channel.
Jira NVGPU-1149
Change-Id: Id9d65841f09459e7acfc8c4ce4c6de7db054dbd8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925427
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Simplify object ownership by passing the gr_ctx mem around directly
instead of reading from tsg via a channel; the caller holds the gr_ctx
already. Also make the function a pure getter; the id is stored by the
caller.
Jira NVGPU-1149
Change-Id: Ia53fbd9ba3bbe7026126382cdea1749f5e02ae57
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822027
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MISRA rule 12.2 states that the right hand operand of a shift
operator shall lie in the range zero to one less than the width
in bits of the essential type of the left hand operand. This
patch will fix these violations in posix code by casting them
to an appropriate type or using the relevant BITxx() macros.
JIRA NVGPU-666
Change-Id: Ibc428ee71977685f413ca0f972efeff34268da62
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954303
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Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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MISRA rule 8.2 requires that all function prototypes have
return type mentioned and have named parameters. The prototype
for sort function is in violation of this rule. This patch will
fix the same by naming the parameters.
JIRA NVGPU-861
Change-Id: I493d36e9d83234233da1d3d65d0e4ce4881d026d
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1947843
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Currently, we assume the VBIOS base ROM size is 64KB. We use
this hardcoding to determine when the bios offset lies beyond
the Base ROM.
This assumption fails on Turing when we try to parse the
clock programming tables which are present in expansion ROM
but have an offset < 64KB.
Remove the hardcoding by storing the base rom size.
Also, replace some magic numbers with macros for readability.
Bug 200455202
Change-Id: Ic4b8c113cfb5ee3e860f7692f5851cdd0ab45d50
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955973
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Instead of just the base address of the main register range, store
(also) the base address of usermode area. All regs may not be always
available; on vgpu guests we have only the usermode regs.
Store the usermode addr we get from a platform resource directly in
gv11b_vgpu_probe() for vgpu. In that case the main reg addr is unset.
The base address is computed in gk20a_pm_finalize_poweron() for native
environments; when the reg addr is read from a resource, the chip is
still unknown and as such the HAL op for reading the usermode base
offset is unavailable.
Bug 200145225
Bug 200467197
Change-Id: I8855bb54a6456eb63b69559c84398f7eeaec3513
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951524
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vgpu gv11b advertises IO coherence with NVGPU_SUPPORT_IO_COHERENCE. Turn
on NVGPU_USE_COHERENT_SYSMEM so that nvgpu internals choose the correct
flag as well; we already set both for native environments together.
Most likely the availability of IO coherence should be read somewhere
instead of hardcoding these flags though.
Bug 200145225
Bug 200467197
Change-Id: Ia1f7b75fdcc230b92aedd50ba1aa0416786a9ed3
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951462
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- For debugging events to user we need a
separate logging type for QNX. This is required
as earlier we were using nvhost logging APIs
but now we are removing all dependency from
nvhost. Linux too can use this type if required.
Change-Id: I57a2a566be9208bb444cba72645eda06acc3d496
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955222
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
While sim code does not need to be MISRA-compliant this
change switches over all memcpy() uses to nvgpu_memcpy()
with appropriate casts applied to maintain consistency within
the nvgpu source base.
JIRA NVGPU-849
Change-Id: Ie0313e2902fffe2acfca714a2ced034406258a75
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946264
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This unit test covers the page_table map/unmap logic as well
as low level PDE/PTE handling.
This patch contains a first phase aiming to cover most
functionality and code coverage but it does not cover
most error handling cases nor formal requirements.
JIRA NVGPU-907
Change-Id: I3b63cfce6cee27d01e1ef54c763560a542992d33
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950974
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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The problem here, and the solution, requires some background
so let's start there.
During page table programming page directories (PDs) are
allocated as needed. Each PD can range in size, depending on
chip, from 256 bytes all the way up to 32KB (gk20a 2-level
page tables).
In HW, two distinct PTE sizes are supported: large and small.
The HW supports mixing these at will. The second to last level
PDE has pointers to both a small and large PD with
corresponding PTEs. Nvgpu doesn't handle that well and as a
result historically we split the GPU virtual address space
up into a small page region and a large page region. This
makes the GMMU programming logic easier since we now only have
to worry about one type of PD for any given region.
But this presents issues for CUDA and UVM. They want to be
able to mix PTE sizes in the same GPU virtual memory range.
In general we still don't support true dual page directories.
That is page directories with both the small and large next
level PD populated. However, we will allow adjecent PDs to
have different sized next-level PDs.
Each last level PD maps the same amount. On Pascal+ that's
2MB. This is true regardless of the PTE coverage (large or
small). That means the last level PD will be different in
size depending on the PTE size.
So - going back to the SW we allocate PDs as needed when
programming the page tables. When we do this allocation we
allocate just enough space for the PD to contain the
necessary number of PTEs for the page size. The problem
manifests when a PD flips in size from large to small PTEs.
Consider the following mapping operations:
map(gpu_va -> phys) [large-pages]
unmap(gpu_va)
map(gpu_va -> phys) [small-pages]
In the first map/unmap we go and allocate all the necessary
PDs and PTEs to build this translation. We do so assuming a
large page size. When unmapping, as an optimzation/quirk of
nvgpu, we leave the PDs around. We know they may well be used
again in the future.
But if we swap the size of the mapping from large to small
then we now need more space in the PD for PTEs. But the logic
in the GMMU coding assumes if the PD has memory allocated then
that memory is sufficient. This worked back when there was no
potential for a PD to swap in page size. But now that there is
we have to re-allocate the PD doesn't have enough space for
the required PTEs.
So that's the fix - reallocate PDs when they require more
space than they currently have.
Change-Id: I9de70da6acfd20c13d7bdd54232e4d4657840394
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933076
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Enable the unified address space config for
o gp10b
o gv11b
gm20b is suffering from a problem in a T214 MODS test. This should
work for the time being in more recent chips. Also this will
increase the soak time these changes get before being released.
Other chips (vGPUs, dGPUs) will (possibly) be enabled at a later
date.
Bug 200105199
Change-Id: I03a6803c6369d89e8a318886fc642b55c5538dd9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951858
Reviewed-by: Automatic_Commit_Validation_User
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I2e7ad84751aa8b7e55946bb1f7e15e4af4cbf245
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827823
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