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gpu: nvgpu: Fix MISRA 12.2 misc bit shift errors

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MISRA rule 12.2 states that the right hand operand of a shift
operator shall lie in the range zero to one less than the width
in bits of the essential type of the left hand operand. This
patch will fix these violations in posix code by casting them
to an appropriate type or using the relevant BITxx() macros.

JIRA NVGPU-666

Change-Id: Ibc428ee71977685f413ca0f972efeff34268da62
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954303
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Srirangan Madhavan
2018-11-20 10:40:43 +05:30
committed by mobile promotions
parent 176668a17d
commit 50d9eb1554
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/nvgpu/include/nvgpu/timers.h
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@@ -74,8 +74,8 @@ struct nvgpu_timeout {
/*
* Bits 1 through 7 are reserved; bits 8 and up are flags:
*/
#define NVGPU_TIMER_NO_PRE_SI (0x1 << 8)
#define NVGPU_TIMER_SILENT_TIMEOUT (0x1 << 9)
#define NVGPU_TIMER_NO_PRE_SI BIT32(8)
#define NVGPU_TIMER_SILENT_TIMEOUT BIT32(9)
#define NVGPU_TIMER_FLAG_MASK (NVGPU_TIMER_RETRY_TIMER | \
NVGPU_TIMER_NO_PRE_SI | \