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gpu: nvgpu: clk fll boardobj update

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Modify clk fll members to support PS3.5
Set b_dvco_1x to true.
Set regime_id_override to FFR as we dont have VFE yet.
Add CTRL_CLK_DOMAIN_HOSTCLK as a valid domain.

JIRA NVGPU-1177

Change-Id: I788ff5a267afd45160be77e9be18a3523d570835
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929832
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951950
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-10-18 17:03:29 +05:30
committed by mobile promotions
parent 8daac563ce
commit 6583c100e2
1 changed files with 12 additions and 1 deletions
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13
drivers/gpu/nvgpu/clk/clk_fll.c
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@@ -352,7 +352,14 @@ static int devinit_get_fll_device_table(struct gk20a *g,
CTRL_CLK_FLL_REGIME_ID_FFR;
fll_dev_data.regime_desc.fixed_freq_regime_limit_mhz =
(u16)fll_desc_table_entry.ffr_cutoff_freq_mhz;
fll_dev_data.regime_desc.target_regime_id_override=0;
if (fll_desc_table_entry.fll_device_type == 0x1U) {
fll_dev_data.regime_desc.target_regime_id_override = 0U;
fll_dev_data.b_dvco_1x = false;
} else {
fll_dev_data.regime_desc.target_regime_id_override =
CTRL_CLK_FLL_REGIME_ID_FFR;
fll_dev_data.b_dvco_1x = true;
}
/*construct fll device*/
pfll_dev = construct_fll_device(g, (void *)&fll_dev_data);
@@ -377,6 +384,8 @@ u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain)
return CTRL_CLK_DOMAIN_SYSCLK;
} else if (vbios_domain == 5U) {
return CTRL_CLK_DOMAIN_NVDCLK;
} else if (vbios_domain == 9U) {
return CTRL_CLK_DOMAIN_HOSTCLK;
}
return 0;
}
@@ -445,6 +454,7 @@ static struct fll_device *construct_fll_device(struct gk20a *g,
nvgpu_memcpy((u8 *)&board_obj_fll_ptr->regime_desc,
(u8 *)&pfll_dev->regime_desc,
sizeof(struct nv_pmu_clk_regime_desc));
board_obj_fll_ptr->b_dvco_1x=pfll_dev->b_dvco_1x;
boardobjgrpmask_e32_init(
&board_obj_fll_ptr->lut_prog_broadcast_slave_mask, NULL);
@@ -483,6 +493,7 @@ static int fll_device_init_pmudata_super(struct gk20a *g,
pfll_dev->min_freq_vfe_idx;
perf_pmu_data->freq_ctrl_idx = pfll_dev->freq_ctrl_idx;
perf_pmu_data->b_skip_pldiv_below_dvco_min = pfll_dev->b_skip_pldiv_below_dvco_min;
perf_pmu_data->b_dvco_1x = pfll_dev->b_dvco_1x;
nvgpu_memcpy((u8 *)&perf_pmu_data->lut_device,
(u8 *)&pfll_dev->lut_device,
sizeof(struct nv_pmu_clk_lut_device_desc));