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gpu:nvgpu: Update clock domain header

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-Update clock domain boardobj header to 0x35 for PS3.5
 and use 0x30 for older P State versions
-Update software setup to build 35 tables.

JIRA NVGPU-1151

Change-Id: Ibedde271474dd24ddeb5657a852fbbb6faee27f8
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917998
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaikundanathan S
2018-10-03 13:35:13 +05:30
committed by mobile promotions
parent 74baefc6f1
commit 8daac563ce
2 changed files with 41 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/gpu/nvgpu/clk/clk_domain.c
View File

@@ -141,7 +141,7 @@ static int _clk_domains_pmudatainit_3x(struct gk20a *g,
pset->vbios_domains = pdomains->vbios_domains;
pset->cntr_sampling_periodms = pdomains->cntr_sampling_periodms;
pset->version = CLK_DOMAIN_BOARDOBJGRP_VERSION;
pset->version = pdomains->version;
pset->b_override_o_v_o_c = false;
pset->b_debug_mode = false;
pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity;
@@ -194,6 +194,8 @@ int clk_domain_sw_setup(struct gk20a *g)
struct clk_domain *pdomain;
struct clk_domain_3x_master *pdomain_master;
struct clk_domain_3x_slave *pdomain_slave;
struct clk_domain_35_master *pdomain_master_35;
struct clk_domain_35_slave *pdomain_slave_35;
u8 i;
nvgpu_log_info(g, " ");
@@ -246,6 +248,7 @@ int clk_domain_sw_setup(struct gk20a *g)
BOARDOBJGRP_FOR_EACH(&(pclkdomainobjs->super.super),
struct clk_domain *, pdomain, i) {
pdomain_master = NULL;
pdomain_master_35 = NULL;
if (pdomain->super.implements(g, &pdomain->super,
CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG)) {
status = boardobjgrpmask_bitset(
@@ -255,6 +258,15 @@ int clk_domain_sw_setup(struct gk20a *g)
}
}
if (pdomain->super.implements(g, &pdomain->super,
CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG)) {
status = boardobjgrpmask_bitset(
&pclkdomainobjs->prog_domains_mask.super, i);
if (status != 0) {
goto done;
}
}
if (pdomain->super.implements(g, &pdomain->super,
CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER)) {
status = boardobjgrpmask_bitset(
@@ -264,6 +276,15 @@ int clk_domain_sw_setup(struct gk20a *g)
}
}
if (pdomain->super.implements(g, &pdomain->super,
CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER)) {
status = boardobjgrpmask_bitset(
&pclkdomainobjs->master_domains_mask.super, i);
if (status != 0) {
goto done;
}
}
if (pdomain->super.implements(g, &pdomain->super,
CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE)) {
pdomain_slave =
@@ -275,6 +296,17 @@ int clk_domain_sw_setup(struct gk20a *g)
pdomain_master->slave_idxs_mask |= BIT(i);
}
if (pdomain->super.implements(g, &pdomain->super,
CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE)) {
pdomain_slave_35 =
(struct clk_domain_35_slave *)pdomain;
pdomain_master_35 =
(struct clk_domain_35_master *)
(CLK_CLK_DOMAIN_GET((g->clk_pmu),
pdomain_slave_35->slave.master_idx));
pdomain_master_35->master.slave_idxs_mask |= BIT(i);
}
}
done:
@@ -322,6 +354,7 @@ static int devinit_get_clocks_table_35(struct gk20a *g,
} clk_domain_data;
nvgpu_log_info(g, " ");
pclkdomainobjs->version = CLK_DOMAIN_BOARDOBJGRP_VERSION_35;
nvgpu_memcpy((u8 *)&clocks_table_header, clocks_table_ptr,
VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09);
@@ -528,6 +561,7 @@ static int devinit_get_clocks_table_1x(struct gk20a *g,
} clk_domain_data;
nvgpu_log_info(g, " ");
pclkdomainobjs->version = CLK_DOMAIN_BOARDOBJGRP_VERSION;
nvgpu_memcpy((u8 *)&clocks_table_header, clocks_table_ptr,
VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07);
@@ -1150,7 +1184,7 @@ static int clk_domain_construct_35_prog(struct gk20a *g,
(struct clk_domain_35_prog *)pargs;
int status = 0;
ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG);
ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG);
status = clk_domain_construct_3x(g, ppboardobj, size, pargs);
if (status != 0)
{
@@ -1159,6 +1193,9 @@ static int clk_domain_construct_35_prog(struct gk20a *g,
pdomain = (struct clk_domain_35_prog *)(void*) *ppboardobj;
pdomain->super.super.super.super.type_mask |=
BIT(CTRL_CLK_CLK_DOMAIN_TYPE_35_PROG);
pdomain->super.super.super.super.pmudatainit =
clk_domain_pmudatainit_35_prog;

2
drivers/gpu/nvgpu/clk/clk_domain.h
View File

@@ -30,6 +30,8 @@
#include <nvgpu/boardobjgrpmask.h>
#define CLK_DOMAIN_BOARDOBJGRP_VERSION 0x30
#define CLK_DOMAIN_BOARDOBJGRP_VERSION_35 0x35
#define CLK_TABLE_HAL_ENTRY_GP 0x02
#define CLK_TABLE_HAL_ENTRY_GV 0x03