Commit Graph

16 Commits

Author SHA1 Message Date
Scott Long
38dee046b0 gpu: nvgpu: more nvgpu_memcpy changes
MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs to
qualified/unqualified types.

To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.

This change switches over non-offending memcpy() uses in gr/pmu/volt
code to nvgpu_memcpy() with appropriate casts applied to maintain
consistency within the nvgpu source base.

Also fixed a Rule 8.3 violation in vfe_var.c by sync'ing the param
names between declarations of the devinit_get_vfe_var_table()
routine.

JIRA NVGPU-849

Change-Id: I004b461988bd3a26212b6fbf660ee7fa742ea1ba
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1952984
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-26 16:35:17 -08:00
Sai Nikhil
692841ca56 gpu: nvgpu: BIOS_GET_FIELD changes
The BIOS_GET_FIELD() macro does a simple bit mask and shift operation.
The value of this macro is assigned to variables of different data
types. Casting the macro to different data types causes MISRA rule
10.8 violations. This issue is resolved by doing the cast inside the
macro and returning the value in the correct data type. These changes
also clear MISRA rule 10.1, 10.3 and 10.4 violations.

JIRA NVGPU-992
JIRA NVGPU-1006
JIRA NVGPU-1010

Change-Id: I16345865d107f0ff0b34daa8b17d7d576eafcfbf
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936357
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-26 11:55:09 -08:00
Mahantesh Kumbar
7672890f48 gpu:nvgpu: Add Change Sequencer
Add change sequencer for PS3.5
Add HAL to select if change sequencer is neeeded.
Add calls from pstate.c to change sequence sw and pmu setup.

JIRA NVGPU-1157

Change-Id: I0722c4bf875577ba04f56f49f21cb1a149b1d37b
Reviewed-on: https://git-master.nvidia.com/r/1929788
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950409
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-24 00:34:04 -08:00
smadhavan
503b897b45 gpu: nvgpu: Fix MISRA rule 8.3 violations
MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the prototype parameter.

JIRA NVGPU-847

Change-Id: I980ca7ba8adc853de9c1b6f6c7e7b3e4ac12f88e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926980
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-15 15:35:47 -08:00
Terje Bergstrom
154ef32dc3 gpu: nvgpu: Remove pmu_perf.h dependency from gk20a.h
gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.

Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.

JIRA NVGPU-596

Change-Id: I2442eba6231c52cca2db0f0ed42cf0a419bc4c10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945307
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-14 13:33:47 -08:00
Terje Bergstrom
07760eb9a1 gpu: nvgpu: Remove clk.h dependency from gk20a.h
gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.

Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.

JIRA NVGPU-596

Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945286
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-11-14 13:33:38 -08:00
Amurthyreddy
b68e465fab gpu: nvgpu: MISRA 10.1 boolean fixes
MISRA rule 10.1 doesn't allow the usage of non-boolean variables as
booleans. Fix violations where a variable of type non-boolean is used
as a boolean.

JIRA NVGPU-646

Change-Id: If451037ada9a5f41b0cddb50778de57f60864f5c
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1815742
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-13 09:45:07 -08:00
Amurthyreddy
3e6779d554 gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.

JIRA NVGPU-1019

Change-Id: I36494e84ee6cd4a108e2a539f48f102e47e2f7f4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926820
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-09 18:46:44 -08:00
Terje Bergstrom
d6a9b1dae1 gpu: nvgpu: Move gv100 perf policy to pmu_perf
While code communicating with PMU perf got moved to pmu_perf, the
file implementing gv100 specifics got left behind. Move that, to
pmu_perf, too.

JIRA NVGPU-596

Change-Id: I2b59970ca60fee8c6c1f19b54dcebfb65c1fde80
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1944887
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-11-09 13:28:45 -08:00
Terje Bergstrom
810317fadc gpu: nvgpu: Move ctrl header files to include/nvgpu/pmuif
pmuif structures refer to the ctrl structures, so that means that ctrl
structures are part of the pmuif. Move the headers to the right place
and update all include statements to include from the right place.

JIRA NVGPU-596

Change-Id: I7be1a727be654d58eccd0e12d599979687dd0733
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1934022
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-01 17:16:03 -07:00
Nicolas Benech
8580a6333c gpu: nvgpu: Fix LibC MISRA 17.7 in PMU
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in PMU files.

JIRA NVGPU-1036

Change-Id: Ie189acf13007f79a1046e8723cdec5b878d4ccc4
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929904
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-01 17:15:40 -07:00
Scott Long
68a042c8d4 gpu: nvgpu: MISRA 21.15 fixes to pmu_perf code
MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.

To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.

This change switches all offending uses of memcpy() in pmu_perf/*.c
code over to use nvgpu_memcpy() with appropriate casts applied.

JIRA NVGPU-849

Change-Id: Iac5e0b1d460f094e950dd4e34e9ccf6a5b0a9edc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939421
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-30 16:11:40 -07:00
Adeel Raza
dc37ca4559 gpu: nvgpu: MISRA fixes for composite expressions
MISRA rules 10.6, 10.7, and 10.8 prevent mixing of types in composite
expressions. Resolve these violations by casting variables/constants to
the appropriate types.

Jira NVGPU-850
Jira NVGPU-853
Jira NVGPU-851

Change-Id: If6db312187211bc428cf465929082118565dacf4
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1931156
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-25 11:13:38 -07:00
Terje Bergstrom
7dc15d6d33 gpu: nvgpu: Move boardobj to common
Move boardobj unit to live under common. It's common code. Also moves
the header files to include/nvgpu/ to indicate that they're meant to
be called from outside boardobj unit.

JIRA NVGPU-596

Change-Id: I57758371c47083e3f666e0cc6d05c48c6d070529
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850419
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-19 17:24:58 -07:00
Sai Nikhil
25aa0f33b1 gpu: nvgpu: pmu_perf: fix MISRA 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: If80c848a47455e631187669b9a67f444dab1e5bc
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921503
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-18 03:25:09 -07:00
Deepak Nibade
b96a6506d0 gpu: nvgpu: rename PMU perf unit to pmu_perf
Move all files under perf/* to pmu_perf/* since pmu_perf is logically
appropriate name for PMU's perf unit
Rename perf.c to pmu_perf.c

Also rename the HAL from gops.perf to gops.pmu_perf

Jira NVGPU-1102

Change-Id: I79e73b8b102ddf6b49783c2f38d861cd43b0b4c6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1819301
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-09-25 13:57:52 -07:00