Commit Graph

8 Commits

Author SHA1 Message Date
Terje Bergstrom
10d3259cdb gpu: nvgpu: Remove thrm.h dependency from gk20a.h
gk20a.h depends on definition of struct therm_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.

Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.

JIRA NVGPU-596

Change-Id: I67010a979ed7f874070796dd834b9b3d1d9dad4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946661
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-14 13:33:57 -08:00
Amurthyreddy
a39c48e3e2 gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.

JIRA NVGPU-1019

Change-Id: I9e18ffc961d485225732c34d3ca561e84d182d07
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921370
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-31 19:35:07 -07:00
smadhavan
3c3f80a687 gpu: nvgpu: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in nvgpu by
renaming them to follow the convention,'NVGPU_PARENT-DIR_HEADER-NAME'
when there is no keyword repetition between file name and directory
or 'NVGPU_HEADER-NAME' when there is repetition.

JIRA NVGPU-1028

Change-Id: I8a473c6c1a864f3893920d8e06e305095e523d2a
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809082
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-09-24 21:17:42 -07:00
Philip Elcan
7f8226887c gpu: nvgpu: cleanup return types for MISRA 10.3
This is a big cleanup of return types across a number of modules in the
nvgpu driver. Many functions were returning u32 but using negative
return codes. This is a MISRA 10.3 violation by assigning signed values
to a u32.

JIRA NVGPU-647

Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810743
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-09-06 21:33:50 -07:00
Terje Bergstrom
7885500a42 gpu: nvgpu: Change license for common files to MIT
Change license of OS independent source code files to MIT.

JIRA NVGPU-218

Change-Id: I1474065f4b552112786974a16cdf076c5179540e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565880
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-09-26 11:37:32 -07:00
Lakshmanan M
d06966c4d9 gpu: nvgpu: Add thermal alert event handling
* Added the thermal alert event handling
* Added the thermal alert event PMU RPC

JIRA DNVGPU-130
Bug 200231080

Change-Id: I54ab0dc35a940e70733238fd95669db28389619a
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1248968
(cherry picked from commit a20593c89a374d64201e4720552160a65533ecc3)
Reviewed-on: http://git-master/r/1282076
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-01-10 03:55:05 -08:00
Lakshmanan M
3621d35f95 gpu: nvgpu: Add PMU thermal RPC for WARN_TEMP
Added PMU thermal slct RPC handling for WARN_TEMP threshold
configuration.

JIRA DNVGPU-130

Change-Id: Iac96557080907bd091217fe983d6a951d0be1da4
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1242133
(cherry picked from commit 8bca85490e716b974315093c47d0d54ec5fb7e0f)
Reviewed-on: http://git-master/r/1246213
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:26:51 +05:30
Lakshmanan M
58b85dd106 gpu: nvgpu: Add thermal module support
The following CL contains the following VBIOS thermal table parsing
and PMU interface support.
1) Thermal device table
2) Thermal channel table

JIRA DNVGPU-130

Change-Id: Ie3abab4bf099a022b1b59db96811c2ed44079519
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1240630
(cherry picked from commit 814962a4be0a8cd0cddc7bc5211c62308ab1fea2)
Reviewed-on: http://git-master/r/1246210
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:26:51 +05:30