Commit Graph

13 Commits

Author SHA1 Message Date
Konsta Holtta
5991f6b856 gpu: nvgpu: pass gr_ctx to map_global_ctx_buffers
Simplify object ownership by passing the gr_ctx around directly instead
of reading from tsg via a channel; the caller holds the gr_ctx already.
Also pass the channel vm and vpr flag instead of the whole channel as
only those are needed.

Jira NVGPU-1149

Change-Id: Ic0921ccaf65f208105b25f08f8d7b581a56b40fe
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-23 04:32:28 -08:00
Konsta Holtta
ca632a2e66 gpu: nvgpu: pass gr_ctx to commit_global_ctx_buffers
Simplify object ownership by passing the gr_ctx around directly instead
of reading from tsg via a channel; the caller holds the gr_ctx already.

Jira NVGPU-1149

Change-Id: I710afc48c0ed11b727cc1b9b6f440110aa404693
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925430
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-23 04:32:19 -08:00
Amulya
999eabbcd7 gpu: nvgpu: MISRA 10.1 boolean fixes
MISRA rule 10.1 doesn't allow the usage of non-boolean variables as
booleans.

Fix violations where a variable of type non-boolean is used as a
boolean and changed few instances of BIT() to BIT32() or BIT64().

JIRA NVGPU-646

Change-Id: I100606a69717c12839aa9c35e7bf6c18749db56e
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809836
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-11-09 13:27:04 -08:00
Deepak Nibade
e059f3cb12 gpu: nvgpu: add separate unit for netlist
All the netlist parsing code is currently under GR unit, but netlist
ucode parsing does not really have any logical dependency to GR

Hence separate out a new unit common/netlist/ that parses the netlist
image and stores/exposes its content through netlist_vars structure

Structure nvgpu_netlist_vars is added to structure gk20a

Move netlist parsing code to common/netlist/netlist.c and chip
specific files to common/netlist/netlist_<chip>.c
Move simulation netlist parsing to common/netlist/netlist_sim.c

Rename g.ops.gr_ctx HAL to g.ops.netlist

Rename all the exported structures to be in the form of nvgpu_*
Rename all exported functions to be in the form of nvgpu_netlist_*()

Add netlist initialization to GPU boot path, and add deinitialization
to GPU remove path

Jira NVGPU-1317

Change-Id: I9af86e3b3230a89db5260cc8ed96ff5f72938c9a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936454
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2018-10-31 09:00:49 -07:00
Konsta Holtta
b08c613402 gpu: nvgpu: make gr_ctx a pointer in tsg
Remove a dependency to a graphics type in tsg header by adding a pointer
indirection.

Jira NVGPU-967
Jira NVGPU-1149

Change-Id: I9177e6eedf08bfe4a3b981b67fa8d4d734f9e50f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822023
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-10-30 05:54:10 -07:00
Adeel Raza
ae093ba07c gpu: nvgpu: simplify addr calc for ctx buffers
Simplify the address calculation for comitting global ctx buffers.

Jira NVGPU-850
Jira NVGPU-853
Jira NVGPU-851

Change-Id: I42924b0bb54a98e58b3eedd248f2ccd6c8f8bb2f
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933833
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2018-10-25 11:13:42 -07:00
Debarshi Dutta
6c8be7cfe2 gpu: nvgpu: move header location of gk20a.h
Change path corresponding to gk20a.h to <nvgpu/gk20a.h> corresponding
to files in the following directories.

gk20a/
vgpu/
gv100/
tu104/
common/bus/
common/fb/
common/ltc/
common/mc/
common/perf/

Jira NVGPU-597

Change-Id: I7b4f5e5ea3d13a4d1810c5db35fbc26fe5da443e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1846826
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-24 23:16:10 -07:00
Akash Goel
e3653e7b5e gpu: nvgpu: tu104: remove smpc extended buffer workaround
In Turing, SMPC gets fe2all_freeze, so extended buffer workaround
is not needed. This workaround has been removed from Ucode, but
not from kernel, this causes smpc counters to either not start or
not stop in some cases.

Bug 2420353

Change-Id: Idb0ddbc4488031b78678adeccb6d77d1b28e0c70
Signed-off-by: akgoel <akgoel@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1931362
(cherry picked from commit 00d813d0a04ce77a18801a1adf8733a52ba769f0)
Reviewed-on: https://git-master.nvidia.com/r/1932436
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2018-10-24 17:01:48 -07:00
Vinod G
9e2d3cce1e gpu: nvgpu: tu104: Support QUAD derivative for 2D
Add support for NV_PTPC_PRI_SM_DISP_CTRL_
COMPUTE_SHADER_QUAD register programming for
graphics

JIRA NVGPUT-135

Change-Id: If0afbf679069eb94ea4d56f8d62c2f21eaee6cf0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928524
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2018-10-24 17:00:55 -07:00
Amurthyreddy
c94643155e gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.

JIRA NVGPU-1019

Change-Id: I8c9ad786a741b78293d0ebc4e1c33d4d0fc8f9b4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921260
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-10-22 08:53:34 -07:00
Terje Bergstrom
3bda3a0678 Revert "Revert "gpu: nvgpu: add turing support""
This reverts commit 278842d6ff4e15467e0b8761c6e1b2a05f926f91.

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I37f47c137c048ddc3a728e143b6f30be525de120
Reviewed-on: https://git-master.nvidia.com/r/1918622
2018-10-12 17:35:09 +05:30
David Gilhooley
b74a4dbd26 Revert "gpu: nvgpu: add turing support"
This reverts commit 27686d8b56316c7ad772dd91548e91516d59f3b1.

Change-Id: Iebda705858edbd58c10ca3024a4ad060401485b6
Signed-off-by: David Gilhooley <dgilhooley@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918612
2018-10-12 17:35:09 +05:30
Deepak Nibade
51244d6112 gpu: nvgpu: add turing support
Add Turing specific common, unit, hardware header files

Make all the Makefile and Makefile.sources changes to compile
all Turing specific code

Bug 200454999

Change-Id: I62ebff5c078b4b8817fc83ea0e4ee3cfffe668dc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917983
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2018-10-12 17:35:09 +05:30