Renamed
- gk20a_tsg_set_runlist_interleave -> nvgpu_tsg_set_interleave
Moved set_interleave from runlist to tsg
- runlist.set_interleave -> tsg.set_interleave
Existing HAL was only setting tsg->interleave, and was not
accessing any register. This is now done in nvgpu_tsg_set_interleave
and tsg.set_interleave is only used in vgpu case.
Jira NVGPU-3156
Change-Id: I5dac1305afcbd950214316289cf704ee8b43fc89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100610
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Moved the following HALs from fifo to tsg:
- tsg.bind_channel
- tsg.unbind_channel
- tsg.unbind_channel_check_hw_state
- tsg.unbind_channel_check_ctx_reload
- tsg.unbind_channel_check_eng_faulted
bind_channel and unbind_channel HALs are optional,
and only implemented for vgpu:
- vgpu_tsg_bind_channel
- vgpu_tsg_unbind_channel
Moved the following code from fifo to tsg:
- nvgpu_tsg_bind_channel
- nvgpu_tsg_unbind_channel
- nvgpu_tsg_unbind_channel_check_hw_state
- nvgpu_tsg_unbind_channel_check_ctx_reload
- gv11b_tsg_unbind_channel_check_eng_faulted
tsg is now explictly passed to bind/unbind operations,
along with ch
Jira NVGPU-2979
Change-Id: I337a3d73ceef5ff320b036b14739ef0e831a28ee
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084029
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Moved enable/disable HALs from fifo to tsg:
- tsg.enable
- tsg.disable
gk20a_tsg_enable and gv11b_tsg_enable are moved to HAL,
since they are chip specific, even though they do not
directly access chip registers.
Removed vgpu_gv11b_tsg_enable as it was identical to
gv11b_tsg_enable.
Changed gv11b_fifo_locked_abort_runlist_active_tsgs and
gv11b_fifo_teardown_ch_tsg to use tsg.enable HAL instead
of calling directly gk20a_disable_tsg HAL implementation.
Jira NVGPU-2979
Change-Id: I721650c64dcf8cd158652e362292af45df43819f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083156
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
- "tsg->tgid" is used for getting "pid" of contexts
in FECS trace support.
- "tsg->tgid" was unitialized for virtualized platforms
which was resulting in "pid" to be "0" for all contexts.
- This patch initializes tgid to fix this issue.
Jira NVGPU-1880
Change-Id: I59c30aca4609d61d09c465b7ec39983095af669b
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081759
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Create a new directory fifo under common vgpu path moving all
vgp common fifo files under that directory.
Move vgpu runlist implementations to a new file runlist_vgpu.c
and create corresponding header file.
Also fix lines over 80 chars in fifo_vgpu.c
Jira GVSCI-334
Change-Id: Ic00535b22a6066a0d27435b9a987de7fa701ea05
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011762
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
