MISRA Advisory Directive 4.5 states that identifiers in the same
name space with overlapping visibility should be typographically
ambiguous.
The use of both ASSERT_CONCAT() and ASSERT_CONCAT_() macros in
the implementation of the nvgpu_static_assert() macro violates
this directive.
This change switches ASSERT_CONCAT() to ASSERT_ADD_INFO() and
ASSERT_CONCAT_() to ASSERT_CONCAT() to eliminate the violation.
Jira NVGPU-3178
Change-Id: I2bf232f3b49267f2f9a211d614969cfc60d3983d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2270893
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Following changes are done to common.top code and UT:
1.Change return type for device_info_parse_enum to void as it can never
return non-zero value.
- This is a private HAL and is only called by get_device_info HAL.
- It gets called only for table entry with entry type = enum.
- So there is no error path left.
This helps remove unnecessary branches and get better branch coverage
2. Check if the data parsing function pointers are not NULL before
parsing the device tree. Return error if there are no functions
to interpret the device_info table registers. Add checks for same in
unit test test_get_device_info().
JIRA NVGPU-2204
Change-Id: I8833da7aa58b070d19b50ee17f64362f301bd792
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2269603
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MISRA Advisory Directive 4.5 states that identifiers in the same
name space with overlapping visibility should be typographically
ambiguous.
The uses of 'a'/'__a' and 'b'/'__b' in the implementation of the
min_t() macro are in violation of this directive.
This change switches '__a' to 't_a' and '__b' to 't_b' (where
't_' stands for "typed") to eliminate these violations.
Jira NVGPU-3178
Change-Id: I72394203ae59ba4d64ca5b539943c3efe9660417
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2270879
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MISRA rule 11.2 doesn't allow conversions of a pointer from or to an
incomplete type. These type of conversions may result in a pointer
aligned incorrectly and may further result in undefined behavior.
This patch addresses rule 11.2 violations related to pointers to and
from struct nvgpu_sgl. This patch replaces struct nvgpu_sgl pointers by
void pointers.
Jira NVGPU-3736
Change-Id: I8fd5766eacace596f2761b308bce79f22f2cb207
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267876
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Preempt TSG occurs in non-mission mode, when unbinding channel
from TSG, or aborting TSG. Should a preempt not complete on
engine, we expect other HW safety mechanisms such as FECS
watchdog to detect issues that prevented saving current context.
Add BUG_ON when attempting to recover from preempt timeout,
to make sure we got such error, and sw_quiesce has been
requested.
Jira NVGPU-4230
Change-Id: Ia26a61e703f74eb28d29e72e75664ca4ec97a586
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265082
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gv11b_mm_mmu_fault_handle_mmu_fault_common was calling
gv11b_mm_mmu_fault_handle_mmu_fault_ce for any mmu_engine_id
greater than gmmu_fault_mmu_eng_id_ce0_v().
This include GR engine on gv11b.
Check the range of mmu_fault_id for CEs instead, before
calling gv11b_mm_mmu_fault_handle_mmu_fault_ce.
Jira NVGPU-4511
Change-Id: I28a78872918dc97e0878ef4c116059eaf5d7fa7b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264975
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Device info data format has changed from gp10b to
gv11b, and MMU fault id was incorrectly decoded for GR engine.
Add gv11b_device_info_parse_data HAL to decode device info
data with correct field definitions.
Move gp10b device_info parse data to non-fusa, since
it is not used anymore in safety build.
Jira NVGPU-4511
Change-Id: I2b3f3b5fec977d63a9ad6cfd99c04f375cf997e8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262217
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As a part of refactoring, we need to move the volt unit from perf to pmu
as it belongs there and also move the arbitor specific functions under
CLK_ARB as they will be removed from safety build.
This patch does the following
*Move volt struct from perf to pmu
*Move volt setup from pmu_pstate to volt
*Move clk freq related functions into CLK_ARB
NVGPU-4491
NVGPU-4492
Change-Id: I7180cd12bbf91cc4d2e79b6e2d71c16e494c8ff0
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268215
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add new unit test to cover gops.gr.init.ecc_scrub_reg HAL function
gops.gr.init.ecc_scrub_reg HAL can generate TIMEOUT errors which are
not returned to caller currently. Update this HAL to return int value
for error propagation.
Jira NVGPU-4458
Change-Id: I98f4d5af2ef17cc4301951fec4d660638c8ef72c
Signed-off-by: dnibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265456
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MISRA Advisory Rule 12.1 states that the precedence of operators
within expressions should be made explicit.
This change modifies the min()/max()/min_t() macro implementations
to eliminate these 12.1 violations.
Jira NVGPU-3178
Change-Id: Ibc1b0bc107d128d300ebdec547417dc7ad201446
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267898
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MISRA Advisory Rule 4.9 states that a function should be used in
preference to a function-like macro where they are interchangeable.
This change switches gk20a_from_mm() and gk20a_from_vm() from
macros to static inline functions.
Jira NVGPU-3178
Change-Id: Ie2a7de0196b69d683ade696adf5e4c9412377607
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256273
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Runlist update occurs in non-mission mode, when
adding/removing channel/TSGs. The pending bit
is a debug only feature. As a result logging a
warning is sufficient.
We expect other HW safety mechanisms such as
PBDMA timeout to detect issues that caused pending
to not clear. It's possible bad base address could
cause some MMU faults too.
Worst case we rely on the application level task
monitor to detect the GPU tasks are not completing
on time.
Jira NVGPU-4322
Change-Id: I7233770349db5dfad6904170a1e9a2d5eada70b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265094
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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The disable_syncpoints debugfs knob allows the user to disable syncpt
support at runtime. This knob was incorrectly defined as a u32. Convert
it into a boolean variable.
JIRA NVGPU-3873
Change-Id: If1cfe07fa7b795c0d1b507395bd6e4fa547e3615
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262193
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Clean up a couple of MISRA violations for functions which are not being
compiled in the safety build.
JIRA NVGPU-3873
Change-Id: Iaaf03c9590bc85d5d411b10363c23266df5630c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262191
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Limit macros from the C library's limits.h are not always in the desired
variable type. Cast these macros to the appropriate variable type to fix
MISRA violations.
JIRA NVGPU-3873
Change-Id: Ib06327aaa6cb78e4a5026b8fc4c15ce356140cc4
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262186
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fbpa related functions are not supported on igpu safety. Don't
compile them if CONFIG_NVGPU_DGPU is not set.
Also compile out fb and ramin hals that are dgpu specific.
Update the tests for the same.
JIRA NVGPU-4529
Change-Id: I1cd976c3bd17707c0d174a62cf753590512c3a37
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265402
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Removed BUG_ON statements from gm20b_pbdma_acquire_val, as
condition could never be true. The only overflow that can
happen is in nvgpu_safe_mult_u64.
Compute exponent by shifting timeout (in units of 1024 ns)
until it fits into mantissa. This removes the need to
compute most significant bits, and allows using hw definitions
for mantissa and exponent max values.
Jira NVGPU-3694
Jira NVGPU-4673
Change-Id: Iaf4b5aaafe5b4e759d4e447f76f05f81e201a584
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263650
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Add unit tests to cover the invalid falcon port access, falcon sw init
switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch
coverage.
Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap
as they are needed by LS PMU and VBIOS code. For iGPU safety the
falcon functions needing these will call the HAL APIs directly.
This way we avoid the unreachable code as well. Updated the
prototype of falcon bootstrap HAL API as that doesn't return
any error.
With these changes, we get 100% line coverage for common.falcon unit.
JIRA NVGPU-2214
Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258311
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PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.
Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.
PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.
Update the doxygen for changed functions.
JIRA NVGPU-4439
Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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