Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset. OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.
Jira NVGPU-3545
Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
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Add branch coverage for:
- nvgpu_channel_kill
- nvgpu_channel_close
Also, modified gk20a_free_channel as follows:
- use nvgpu_assert to check ch->g (so that it can be tested)
- make sure g is non-NULL before calling nvgpu_get_poll_timeout
Jira NVGPU-3480
Change-Id: Ie1fa231b022da47b9ef9022ae67a6b3d73c28a8b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129724
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Updated test to cover test where:
- update runlist fails during unbind
- tsg is aborted
- updated runlist fails during abort
Modified update runlist stub to return -EINVAL depending
on branch combinations.
Added custom pruning function to skip some impossible
combinations of non-final branches.
Jira NVGPU-3476
Change-Id: I23a64085239b4003b73873a984a301476d73d962
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124513
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Added coverage for
- nvgpu_tsg_open
- nvgpu_tsg_release
In order to cover branch combinatorial, a bitmask is used.
For each branch, one bit indicates if the branch is taken or not.
A loop calls the tested function with all combinations.
We could afterwards prune some combinations for branches that
directly exit the function.
Set MM_UNIFIED_MEMORY feature to avoid allocating from vidmem.
Jira NVGPU-3476
Change-Id: If2e82eabfa492b4c9ec727e175f31b53fbb4f5f1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123156
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Added pre-populated register space for gv11b:
- NV_FUSE 0x00021fff:0x00021000
Registers values were captured for Xavier on DDPX platform,
using reg_dump, after disabling railgating and ELPG.
Jira NVGPU-3476
Change-Id: Ic96f06501c3e903aef7ed635a88005332758bbb6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120663
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Added pre-populated register spaces for gv11b:
- NV_PCCSR 0x0080FFFF:0x00800000
- NV_PMC 0x00000FFF:0x00000000
- NV_PPBDMA 0x0005FFFF:0x00040000
Registers values were captured for Xavier on DDPX platform,
using reg_dump, after disabling railgating and ELPG.
Also added missing reg space unregistration for NV_TOP.
Jira NVGPU-3476
Change-Id: I8745f820819c1201846472602d7ef1872583ef4e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120657
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Added pre-populated register spaces for gv11b:
- NV_PFIFO 0x00003FFF:0x00002000
- NV_PTOP 0x000227FF:0x00022400
Registers values were captured on DDPX with reg_dump,
after disabling railgating and ELPG.
This allows running nvgpu_fifo_init_support, using
gv11b HALs.
Added the following tests:
- test_fifo_init_support
- test_tsg_open
- test_tsg_release
- test_fifo_remove_support
Jira NVGPU-3476
Change-Id: Ia717d9a9d431248635d51d0c265c16c2b6806a95
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120564
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us
Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us
Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.
Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry
Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.
Added #defines for min, max and default timeslices.
Jira NVGPU-3156
Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
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Add -t/--test-level option for the unit test framework. This
correlates with the test plan levels in GVS. L0 tests are a subset of
the L1 tests. Currently, only test levels 0 and 1 are supported.
The test output has been updated to display skipped tests. Skipped
tests are not included in the test dump.
JIRA NVGPU-2251
Change-Id: Icc2ff19a81529be8526e89f70983e96040390e00
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085280
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The licenses used in the userspace folder were inconsistent.
This patch fixes the situation by ensuring all files are using the
MIT license.
JIRA NVGPU-2974
Change-Id: I8c89667f72732ff6f73e6cf4be1acd9e58a7e516
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087125
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Introduce nvgpu_bitmap_set() and nvgpu_bitmap_clear() APIs to wrap the
bitmap_set() and bitmap_clear() APIs, respectively. The new nvgpu_*
versions accept unsigned length parameters since length is logically an
unsigned value where bitmap_set and bitmap_clear accept signed values.
We inherit bitmap_set and bitmap_clear from the OS, so we can't
directly change those.
Also, change uses of the old APIs to the new ones.
These changes resolve MISRA Rule 10.3 violations for implicit assignment
of objects of different essential or narrower type.
JIRA NVGPU-2953
Change-Id: I2c8f790049232a791f248b350c485bb07452315b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077624
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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This reverts commit ade1d50cbe.
Currently a fifo_runlist_info_gk20a structure is allocated and
initialized for each possible runlist. But only a few runlists
are actually used.
Use an array of pointers to runlists in fifo_gk20a. The array
keeps existing indexing by runlist_id. In this patch a context
is still allocated for each possible runlist, but follow up
patch will allow to skip context allocation for inactive
runlists.
Bug 2470115
Bug 2522374
Change-Id: I0deb6981bc6f5152bdf121f0a44429748aa14687
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030407
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Currently a fifo_runlist_info_gk20a structure is allocated and
initialized for each possible runlist. But only a few runlists
are actually used.
Use an array of pointers to runlists in fifo_gk20a. The array
keeps existing indexing by runlist_id. In this patch a context
is still allocated for each possible runlist, but follow up
patch will allow to skip context allocation for inactive
runlists.
Bug 2470115
Change-Id: I1615043cea84db35a270ade64695d51f85c1193a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025203
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Drop the "runlist_" part in the runlist section of the HAL ops. For
example:
- old: g->ops.runlist.runlist_wait_pending
- new: g->ops.runlist.wait_pending
At the same time, drop the "fifo_" part from the function names. For
example:
- old: gk20a_fifo_runlist_wait_pending
- new: gk20a_runlist_wait_pending
Also rename eng_runlist_base_size to count_max. The size of the
eng_runlist_base register array depicts the maximum possible number of
runlists in the chip for which count_max is more descriptive.
Jira NVGPU-1309
Change-Id: Ie9e94b9f65cd10d3e682d19954f240adb6e311be
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017403
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Extract non-chip-specific code that manages the runlists (init, update,
reschedule etc.) to a new file in the common directory. Move the
declarations to a new matching runlist.h header.
Jira NVGPU-1309
Change-Id: I3c7e0032899516487037f47ddc9a7e7aa4b0b33a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978058
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