Replace all nvgpu_next functions/structs either by 1) collapsing them
into nvgpu legacy functions/structs 2) renaming them as follows:
- nvgpu_next_*() => nvgpu_(ga10b/ga100)_*()
- nvgpu_next_*() => (ga10b/ga100)_*()
- nvgpu_next_*() => nvgpu_*() [only if this doesn't cause collision]
- nvgpu_next_*() = > nvgpu_*_extra()
Create hal.sim unit and move Ampere+ SIM code into it.
Jira NVGPU-4771
Change-Id: I215594a0d0df4bd663bd875a0d0db47bcb9ff6a2
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548056
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.
Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.
Jira NVGPU-4771
Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092
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Created Perfmon events handling for nvgpu-next.
Nvgpu-next pmu send perfmon events in the form of
rpc events. Events are:
- Change event: This gives information of whether
it is increase/decrease event.
- Init event: This gives information of perfmon init
done in PMU.
NVGPU-5202
NVGPU-5205
NVGPU-5206
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ida7e77dbaf70d2b594a0801c91a168dcb4a860bd
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2395358
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IRQs can get triggered during nvgpu power-on due to MMU fault, invalid
PRIV ring or bus access etc. Handlers for those IRQs can't access the
full state related to the IRQ unless nvgpu is fully powered on.
In order to let the IRQ handlers know about the nvgpu power-on state
gk20a.power_on_state variable has to be protected through spinlock
to avoid the deadlock due to usage of earlier power_lock mutex.
Further the IRQs need to be disabled on local CPU while updating the
power state variable hence use spin_lock_irqsave and spin_unlock_-
irqrestore APIs for protecting the access.
JIRA NVGPU-1592
Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203860
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Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.
Allocation happens at pmu early init stage & will deinit at
remove_support stage.
JIRA NVGPU-1972
Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
.pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
.pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,
These were being called by:
g->ops.pmu.pmu_init_perfmon,
g->ops.pmu.pmu_perfmon_start_sampling,
g->ops.pmu.pmu_perfmon_stop_sampling,
g->ops.pmu.pmu_perfmon_get_samples_rpc
Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_perfmon_init(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_start_sampling_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_stop_sampling_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_get_samples_rpc_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
and based on hardware chip call the chip specific
perfmon sw init function: nvgpu_gv11b_perfmon_sw_init() and
nvgpu_gv100_perfmon_sw_init() and assign the sw ops for perfmon
JIRA NVGPU-3210
Change-Id: I2470863f87a7969e3c0454fa48761499b08d445c
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109899
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Created PMU fw unit to hold PMU RTOS f/w specific ops, images,
flags & command arguments needed for PMU RTOS ucode support.
Moved PMU fw ops from gk20a.gpu_ops to pmu.fw.ops as these ops
are needed to support different version of PMU fw version for
different chips
JIRA NVGPU-1955
Change-Id: I51385d8c20524431f07cba3378676464663deb20
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090769
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- Move the perfmon unit source code to common/pmu/perfmon/ folder
- Separate perfmon unit headers under include/nvgpu/pmu/pmu_perfmon.h
- Make a new structure: nvgpu_pmu_perfmon for perfmon unit
- This new struct combines all perfmon unit variables like
perfmon_query, perfmon_ready etc. into one
structure as a part of perfmon unit refactoring.
- Use pmu_perfmon struct to access all perfmon variables.
- Eg: pmu->pmu_perfmon->perfmon_query, pmu->pmu_perfmon->perfmon_ready
and so on.
JIRA NVGPU-1961
Change-Id: I57516c646bfb256004dd7b719e40fafd3c2a09b2
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2080555
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