5 Commits

Author	SHA1	Message	Date
Mahantesh Kumbar	5f8fb9f41a	gpu: nvgpu: Deleting SEC2 HAL's gp106 support ... -Deleting GP106 from SEC2 HAL as GP106 is not supported anymore. JIRA NVGPU-3243 Change-Id: I4cce6169104d18096ff24fa9e4044d5697ad8e8f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2168202 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-08-05 23:01:09 -07:00
Mahantesh Kumbar	3ef34ac31c	gpu: nvgpu: PMU/SEC2/GSP engine reset skip ... -Add a FUSA check to skip reset for PMU/SEC2/GSP engine's falcon -On dGPU FUSA SKU, reset of HS falcons SEC2, PMU and GSP will be handled by HS falcon ucode, so, skip reset for PMU/SEC2/GSP in NvGPU. JIRA NVGPU-3728 Change-Id: I956272771994b96e4115e67869bce7bd03193196 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2163560 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-07-30 07:36:48 -07:00
Sagar Kamble	f6723a5bd7	gpu: nvgpu: compile out igpu non-safe falcon functions ... Following common and corresponding hal functions are non-safe. They are either required for intr handling or for debug. Compile them out for igpu safety release. Moved corresponding HALs to falcon_gk20a.c. nvgpu_falcon_copy_from_emem nvgpu_falcon_copy_to_emem nvgpu_falcon_clear_halt_intr_status nvgpu_falcon_set_irq nvgpu_falcon_copy_from_dmem nvgpu_falcon_copy_from_imem nvgpu_falcon_print_dmem nvgpu_falcon_print_imem nvgpu_falcon_get_ctls nvgpu_falcon_dump_stats can be used in the safety debug build. JIRA NVGPU-898 JIRA NVGPU-2214 Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2152978 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-07-23 10:22:13 -07:00
Sagar Kamble	47b450b250	gpu: nvgpu: address CCM deviations for tu104_sec2_emem_transfer ... tu104_sec2_emem_transfer CCM value was higher than 10. Address through new function sec2_memcpy_params_check by seggregating the parameter checks. JIRA NVGPU-3194 Change-Id: Iaaf08a36cb40b15b3b0f5bfd0cd96c2e00dd4e51 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2101944 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-26 14:18:12 -07:00
Sagar Kamble	0cd90a1167	gpu: nvgpu: move sec2 hal sources to hal/sec2 ... Move sec2_gp106.c and sec2_tu104.c to hal/sec2 as per new unit separation requirements. JIRA NVGPU-2024 JIRA NVGPU-2025 Change-Id: I511e1832aa63d4792729491428de0159decf2371 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085755 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-10 09:27:26 -07:00