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9347 Commits

Author SHA1 Message Date
prsethi
24a533c9dc nvgpu: print the caller name with quiesce 
Currently quiesce method does not print the caller name which makes it
difficult to find the reason behind the issue.

Change prints caller name and invocation line number.

Bug 4098984

Change-Id: I34a0f557c411f997022668e187060c1c1247b15f
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2900585
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-15 15:54:43 -07:00
Martin Radev
d70c9a708b gpu: nvgpu: expose local-to-logical/physical GPC mappings 
Expose the local-to-logical/physical GPC mappings for
devtools needs.

Bug 3944943

Change-Id: I2aa69ccef19627d41f3e2b8dcc9235401ae1f782
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2900289
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-15 06:08:33 -07:00
Austin Tajiri
7522c3ee31 gpu: nvgpu: skip security check in ctxsw init 
Force ctxsw ucode to skip the security level check by clearing mailbox 1
before starting FECS/GPCCS.

Jira NVGPU-9217

Change-Id: Id4286d0882a29a849128e62c5421c8ae6071e3b1
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891013
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-15 06:07:23 -07:00
Austin Tajiri
7e0351f291 gpu: nvgpu: retry MMU fault buffer read 
When handling MMU faults, retry the first MMU fault buffer read multiple
times until it contains valid data. There may be a delay between the MMU
fault interrupt triggering and the fault buffer containing valid data.

Jira NVGPU-9217

Change-Id: I06b442acaf54a4e036795de65345b423f9b424bf
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2881909
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-15 06:07:18 -07:00
Rajesh Devaraj
a321679a5d gpu: nvgpu: add is_gsp_supported flag 
This patch adds is_gsp_supported flag and initializes it for GA10B,
TU104. Further, this flag is checked before initializaing GSP LITE
falcon.

JIRA NVGPU-9983

Change-Id: If0a4a3095c15cac113895f3d114e731f35211c5d
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2902651
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-15 01:19:26 -07:00
Martin Radev
789ebda23d nvgpu: Expose HES PM resource 
This patch adds the HES profiling resource.

Bug 3944963

Change-Id: Ie7ea4d060cfdc6803262166c1c89d0c2d155c9e3
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2901996
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Kishan Palankar <kpalankar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2023-05-12 20:58:19 -07:00
Martin Radev
cad414d310 gpu: nvgpu: Expose NUMA domain id 
This patch exposes the NUMA domain id for the
Linux device to userspace. This information is
necessary for userspace to make better utilization
of physical memory allocation and CPU scheduling.

Bug 3972227

Change-Id: I9ad0369076d22531e154074d616e5a23e374a7e9
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2897294
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-10 06:29:32 -07:00
srajum
80a21343a0 userspace: Enable unit tests on l4t for GA10B 
JIRA NVGPU-9909

Change-Id: I4917384b855ebfe6e3c428f0a268ad09a6bfb573
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2892996
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-09 22:27:09 -07:00
mpoojary
a9b995bc3f gpu: nvgpu: Copy correct struct from RPC payload for pmu acr 
Size of nv_pmu_rpc_struct_acr_bootstrap_gr_falcons is copied from the
RPC payload for pmu acr instead of nv_pmu_rpc_header in pmu rpc handler.
This causes KSAN slab out-of-bounds error.

Bug 3727012

Change-Id: I633dac9167f9ed896dba956dc56e4081aaab6465
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891392
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-09 16:08:42 -07:00
vivekku
bd5ab81ccc gpu: nvgpu: nvs: queue direction update 
Changes:
-  update nvgpu_nvs_ctrl_queue to have queue direction as it is required
by gsp scheduler to erase queue individually
- queue direction is updated during ioctl call to create queue and is
used only by gsp scheduler. So no other moduler should be affected by
it.

- need to pass the size of struct which is u32 so downgrading it from
u64 to u32 is intentional, misra C violation 10.3 can be ignored here

Bug 4027512

Change-Id: I6ef6e4b06124e25da3d004a2d8822516c3ac2105
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2881804
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-08 23:37:56 -07:00
Divya
a4175b1265 gpu: nvgpu: resolve pmu mismatches 
Add the following pmu HALs for PMU registers
to avoid duplication of code for future chips:
- get_bar0_addr
- get_bar0_data
- get_bar0_timeout
- get_bar0_ctl
- get_bar0_error_status
- set_bar0_error_status
- get_bar0_fecs_error
- set_bar0_fecs_error
- get_mailbox
- get_pmu_debug

JIRA NVGPU-9758

Change-Id: If8b9c91ecd51d526babf12e3cee09048d736f0f4
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2897156
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-05 19:48:04 -07:00
Deepak Goyal
811f8546cf nvgpu: sysfs: remove 'allow_all' from prod build 
REG_OPS whitelist can be bypassed using sysfs
/sys/devices/gpu.0/allow_all
Sysfs are privileged, need Root access to set this sysfs.
This node should not be exposed by NVGPU-RM in Linux prod builds.

Bug 4083557

Change-Id: I984212df7a9f2dfeb6759cc502ae485daa1d82d4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2893829
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-05 11:49:28 -07:00
Rajesh Devaraj
01d3ed09b0 gpu: nvgpu: update get_access_map 
This patch re-names the variables used in gr_init_get_access_map API:
whitelist - gr_access_map
num_entries - gr_access_map_num_entries
wl_addr_*[] - gr_access_map_*[]

JIRA NVGPU-9849

Change-Id: I3a0a59410af8983867af5bc2f9ff200e56e190c4
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891567
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-05 02:31:10 -07:00
Shashank Singh
9512b9f1de gpu: nvgpu: remove user managed addr space capability flag 
Remove NVGPU_GPU_IOCTL_ALLOC_AS_FLAGS_USERSPACE_MANAGED and
NVGPU_AS_ALLOC_USERSPACE_MANAGED flags which are used for supporting
userspace managed address-space. This functionality is not implemented
fully in kernel neither going to be implemented in near future.

Jira NVGPU-9832
Bug 4034184

Change-Id: I3787d92c44682b02d440e52c7a0c8c0553742dcc
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882168
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-04 11:39:30 -07:00
Martin Radev
84bb919909 gpu: nvgpu: Setup GFX-capable TPCs 
This patch dispatches to the appropriate HAL to
select the GFX-capable TPCs.

Bug 3944931

Change-Id: Ifb7338bea2cd59581133b7a2ba723f5d8bfa507c
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891725
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-04 11:38:54 -07:00
Divya
c728f09c18 gpu: nvgpu: add sysfs node for golden img status 
- Add a sysfs node "golden_img_status" to show
  if golden_image size and ptr are already initialized
  or not.
- This node helps to know golden image status before
  attempting to modify gpc/tpc/fbp masks.

Bug 3960290

Change-Id: I3c3de69b369bcaf2f0127e897d06e21cb8e2d68e
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868729
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-04 11:36:37 -07:00
prsethi
c49ac865de gpu: nvgpu: init golden ctx image during nvgpu poweron 
Safety build temporal requirement is that on FECS power up it should go
through entire initialization methods.
init_golden_image callback is being called from devctl/ioctl path and
triggers FECS method 10 and 11. As these methods are part of APP init,
not being called during resume and causing quiesce on safety build.
To fix this issue, calling the callback from poweron API.

Bug 4082813
Bug 4037712

Change-Id: I2d27203d3cb4326ae7d8bd6025693fd61d5237df
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2893218
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-04 03:14:19 -07:00
Richard Zhao
be7b4aac61 gpu: nvgpu: linux: pci calls vgpu power on for virt dev 
VF driver shares same poweron function with legacy vgpu.

Jira GVSCI-15779

Change-Id: I44381f7ebe1cfd6c72ff886aa9f54d54c189a8b6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2884178
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-01 00:24:56 -07:00
Richard Zhao
f9242c032e gpu: nvgpu: linux: add virtual function support 
vf probe is called by pci general probe when platform data indicates
it's a virtual device.
vf_linux covers PCIE specific initialization, then call common vgpu
probe.

Jira GVSCI-15779

Change-Id: I47ce1c4807b23363a9062ff0cbc8e08b9c6cdc97
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2884177
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-01 00:24:45 -07:00
Richard Zhao
8a411096c9 gpu: nvgpu: linux: vgpu to use dt_node for tegra_gr_comm 
For PCIE gpu device, it uses PCIE controller dt node to store nvgpu/vgpu
dt properties, since PCIE endpoint device does not have any
corresponding dt node. So we pass dt_node directly to tegra_gr_comm,
together with EP device since tegra_gr_comm relies on dev_err.

Jira GVSCI-15779

Change-Id: I73c5210e2d8b6a728c74823c1e62fed765776365
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2884176
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-by: Santosh BS <santoshb@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-01 00:24:34 -07:00
Richard Zhao
03da61c9ce gpu: nvgpu: vgpu: create vgpu_common file 
vgpu_common file contains common functions that could be shared by
legacy vgpu and vf.

Jira GVSCI-15779

Change-Id: Ie301eb29dfceed95bcd96a1024663f31eb7558fd
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2884175
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-05-01 00:24:28 -07:00
Richard Zhao
678df244b9 gpu: nvgpu: vgpu: remove bar1 support 
All vgpu supported chips don't support bar1 anymore.

Jira GVSCI-15779

Change-Id: Ia2dc4a69f3cb96df6650e663d2a40302fc826dd2
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2884174
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Santosh BS <santoshb@nvidia.com>
Reviewed-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-05-01 00:24:07 -07:00
Johnny Liu
4e6be49eee gpu: nvgpu: Correct the name of devfreq governor 
Remove the duplicated nvhost_pod_scaling_governor_v2 and switch to the
nvhost_pod_scaling_governor.

Bug 4074863

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Change-Id: Ia6016cab46e97f04366d6cf14355b2e7e0989df8
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2895568
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-28 08:10:31 -07:00
Divya
3e5424bee3 gpu: nvgpu: gv11b: ap_compute fix 
- During nvgpu_poweron, PERFMON_INIT RPC and
  ACR_INIT_WPR_REGION command is sent to PMU in two different threads.
- For perfmon RPC method is used and for ACR, CMD-MSG queue is used.
- Since the pmu thread and poweron thread run in parallel, the
  pmu sequence acquired by both can have the same seq_id.
- For Perfmon RPC, nvgpu_pmu_seq_free_release() is called
  followed by nvgpu_pmu_seq_release().
- This causes clearing of sequence for the next command.
- To resolve this, instead of nvgpu_pmu_seq_free_release(),
  just free the rpc-payload after getting ack for perfmon and
  then do sequence release.
- This ensures that the ACR cmd sent just after perfmon RPC does
  not get the same seq_id and the sequence is not cleared.

Bug 4074021

Change-Id: Id9972cb719458062d8c7d9e226a25599026c052b
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2889840
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-28 03:32:42 -07:00
srajum
53941baa93 gpu: nvgpu: fixing unit tests for ga10b 
- Add support for unit tests to run on orin platform.

JIRA NVGPU-9909 

Change-Id: I60a059840fd0d2733b0a1f2b3c1f722f8616868e
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2892228
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-28 02:08:14 -07:00
srajum
b2345cd01a gpu: nvgpu: fixing unit tests for ga10b 
- Add support for unit tests to run on orin platform.

JIRA NVGPU-9909 

Change-Id: If4ca69b77d0d8483c0e9f6a6a5a64c3c3e050d65
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2737876
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-28 02:08:09 -07:00
srajum
63057907ee gpu: nvgpu: Add mock support for all ga10b registers 
- Add support for unit tests to run on orin platform.

JIRA NVGPU-9909

Change-Id: I532e667c4b30c36ca19776cd4ac8ef8fb1147d03
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2886066
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-28 02:08:04 -07:00
Sagar Kamble
4ee71f9852 gpu: nvgpu: guard ecc sysfs remove with NVGPU_DISABLE_ECC_STATS 
Following error is seen on unloading nvgpu on platforms with
NVGPU_DISABLE_ECC_STATS set to true.

[ 3712.384639] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[ 3712.388479] pc : sysfs_remove_file_ns+0x28/0x50
[ 3712.389119] lr : sysfs_remove_file_ns+0x28/0x50
...
[ 3712.400640]  sysfs_remove_file_ns+0x28/0x50
[ 3712.401280]  device_remove_file+0x34/0x50
[ 3712.414720]  nvgpu_ecc_sysfs_remove+0x74/0xc0 [nvgpu]
[ 3712.428800]  nvgpu_ecc_remove_support+0x38/0x80 [nvgpu]
[ 3712.442240]  nvgpu_put+0xb8/0x160 [nvgpu]
[ 3712.456319]  nvgpu_pci_remove+0x168/0x250 [nvgpu]
[ 3712.456959]  pci_device_remove+0x4c/0x100

This is happening as ecc sysfs files are not created, however
their removal is attempted. Add NVGPU_DISABLE_ECC_STATS check
for ecc sysfs removal.

Bug 3495440

Change-Id: I9726cf43a740c2b591ca39bdc572e8f4ff5684d3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891876
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-26 20:08:45 -07:00
Divya
b54cb9fd97 gpu: nvgpu: add pmu hals 
Add the following HALs for following PMU registers:
- get_irqstat
- set_irqsclr
- set_irqsset
- get_exterrstat
- set_exterrstat
- get_exterraddr

JIRA NVGPU-9758

Change-Id: Ib153d3189ff493fdb726ec2d1e81b863476fc667
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2886108
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-21 11:33:56 -07:00
Martin Radev
924dd58da0 gpu: nvgpu: remove IO_COHERENT flag 
This patch removes the IO_COHERENT flag as IO
coherence is the default setting.

Bug 3959027

Change-Id: I9800c2b8b161f7bdc2d6856639dd03488881882d
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2887630
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-21 11:32:05 -07:00
Martin Radev
81d95456b9 gpu: nvgpu: Rename PLATFORM_ATOMIC to SYSTEM_COHERENT 
To support current and future usecases, it would be
beneficial to select the SYSTEM_COHERENT aperture explicitly.

The benefits are:
- platform atomic code is cleaned-up.
- userspace can select the SYSTEM_COHERENT aperture for any
  specific usecases.

Bug 3959027

Change-Id: I6489ebe87fa75cc760930277bad5e0cacca80eb6
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864177
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-21 11:31:53 -07:00
Ramalingam C
24475ad46b gpu: nvgpu: pci power management for iGPU-PCIe devices 
Use the PCI power management functions for iGPU-PCIe devices.

JIRA NVGPU-9896

Change-Id: I1ac4ae67fa727e0a8e37ed2037d1417c5c19bb17
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2886799
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-14 08:20:47 -07:00
Austin Tajiri
24bebfabaf gpu: nvgpu: add engine base vector HALs 
Add HALs for getting the base vectors for stall and nonstall engine
interrupts. The engine interrupt IDs are added to these base vectors
to determine the engine stall and nonstall interrupt vectors.

Jira NVGPU-9217

Change-Id: Ieaf0e75caac0f7e23684b80466fbf1dc3a57f68d
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880426
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-13 22:16:13 -07:00
Shashank Singh
21cb70f58d gpu: nvgpu: remove kind control capability 
Kind is controlled by nvgpu userspace library so related capability
flags can be removed from kernel and uapi interface.

Jira NVGPU-9832
Bug 4034184

Change-Id: Id2b0a4e1cd784638362116b8d99177467fba998b
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880391
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-13 12:21:46 -07:00
Austin Tajiri
56a4680a3b gpu: nvgpu: refactor gr.intr.handle_sw_method 
- Add defintions of the gfx/compute classes and methods that are
  generated from the hw/sw class header files. Use these definitions
  instead of the hard-coded ones so that mismatches may be caught by
  the HAL checker.
- Abstract out the sw method handling functionality of
  gr.intr.handle_sw_method into gr.intr.handle_gfx_sw_method and
  gr.intr.handle_compute_sw_method and have gr.intr.handle_sw_method
  call these two new HALs.

Jira NVGPU-9217

Change-Id: Ia30fcba6174878d9b5b7b5910c564c879a702ddc
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2885547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-13 12:20:33 -07:00
Divya
7a4fff4b17 gpu: nvgpu: add hal for pmu sequence cleanup 
- On older chips, PMU uses CMD-MSG queue method to
  communicate with NvGPU.
- From Turing onwards, PMU uses RPC method for this.
- During poweroff, we release pmu_sequence and reset the
  members of the structure.
- For chips that use RPC, we need to free the payload as well
  and then reset the members.
- Add pmu_seq_cleanup hal for this.

Bug 4019694
Bug 4059157

Change-Id: Ieb474fe4ed81f54d78480214cde53b51d45652c6
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882267
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-12 16:28:52 -07:00
Divya
db9a411a06 gpu: nvgpu: sync free of rpc_payload 
- During driver unload, shutdown or RG path as part of
  pmu destroy, pmu sequences have to be cleaned up to
  free payload memory and allocation info which is stored
  as part of pmu_sequence.
- While doing so there can be race condition with pmu_isr
  or nvgpu_pmu_rpc_execute path where it waits for fw ack.
- This race condition can lead to freeing of payload memory
  before nvgpu_pmu_sequences_cleanup() does.
- This can lead to memory corruption or double free issue
  when the cleanup code again tries to free the payload mem.
- To resolve this add a new function nvgpu_pmu_seq_free_release()
  which will check for seq->id in pmu seq tbl before freeing the
  memory and other info from pmu_sequence.
- Use this nvgpu_pmu_seq_free_release() in non-blocking RPC calls
  and also when fw ack fails or driver is dying scenario.
- For blocking call, synchronise freeing of rpc payload memory by
  using a new boolean seq_free_status.

Bug 4019694
Bug 4059157

Change-Id: Id45a6914a2d383a654539a87861c471a77fb6850
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882210
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-12 16:28:41 -07:00
Ramalingam C
b2c4cdb25b gpu: nvgpu: sim init for iGPU-PCIe 
Implement the sim init for the iGPU-PCIe devices.

JIRA NVGPU-9348

Change-Id: I9088308b96c57bb1cea01959326446ccad0a8c24
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2851163
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-10 20:45:50 -07:00
Prathap Kumar Valsan
d0ed86ab1e gpu: nvgpu: update PT lvl array to six levels 
Increase the size of page table level array to index six levels.

Jira NVGPU-9760

Change-Id: I482639fd028ecd504ee8bc313c39f3bd710e81a9
Signed-off-by: Prathap Kumar Valsan <prathapk@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868918
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-07 21:08:45 -07:00
Kishan
c6d5fb348c gpu: nvgpu: Capture thread name for every channel created 
This change ensures that in scenarios where GPU enters a bad
state because of the work submitted by a misbehaved thread,
we should be able to capture thread name as part of our
1st set of failure logs.
Changes for QNX env is pending.

JIRA NVGPU-7783

Change-Id: I65d55a6ade749ff91739458e0642ed2dafaae5cc
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2879197
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-06 10:12:48 -07:00
Ramalingam C
af48120169 gpu: nvgpu: configure CWD sm id regs before ucode load 
GPCCS ucode is expecting the SM ID programmed in GPM and CWD registers
to be in sync. So create a hal called gr.init.load_sm_id_config()
for the sm_id programming for the CWD registers and invoke them before
the ucode load.

Initialize this hal only for the required GPUs.

JIRA NVGPU-9757

Change-Id: Ib0984fd6326c37e0c2a06123041032575a23ec04
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864999
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-06 10:09:14 -07:00
Timo Alho
3ff15b69de gpu: nvgpu: fix return value check of MRQ_STRAP 
The return value of tegra_bpmp_transfer() API is only for a low level
wire-protocol errors. When checking BPMP-FW response to MRQ_STRAP
request, the return value in the MRQ response payload need to be
checked.

Bug 3744064
Bug 3317279

Signed-off-by: Timo Alho <talho@nvidia.com>
Change-Id: I165431a5d2ed5a09965eb84b7ee09766bb09d091
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859267
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-06 00:41:59 -07:00
Ramalingam C
7ba33f3dec gpu: nvgpu: Handle iGPU in pci probe and remove 
When iGPU is probed as pci device, power and clocks are driven from the
platform, hence the pci_probe and pci_remove to handle both
iGPU and dGPU. Also enable the runtime PM for the PCI-iGPU
device.

JIRA NVGPU-9348

Change-Id: Id5dd88dc0c905655f9174ecd7936bdf2996f06e6
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2835341
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-05 05:53:03 -07:00
Ramalingam C
ebb60b7f5e gpu: nvgpu: Add a flag CONFIG_NVGPU_PCI_IGPU 
To support the pci probe for the integrated GPU, add a new config
flag called CONFIG_NVGPU_PCI_IGPU.

This will help us in compiling the pci related files for igpu safety
builds too

JIRA NVGPU-9348

Change-Id: I1824060db56b2cf555d4ad55bd870f3a20c95741
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2835339
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-05 05:52:52 -07:00
Shashank Singh
28cbdcde73 gpu: nvgpu: remove partial mapping capability flag 
Remove NVGPU_SUPPORT_PARTIAL_MAPPINGS kernel flag and the
corresponding uapi gpu charaacteristics flag
NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS. This functionality is
supported by fixed mapping ioctl by default.

Jira NVGPU-9832
Bug 4034184

Change-Id: Ie887c753f152afb6a4a1e4aafb5f8f6fd3b7b398
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2879793
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-04-04 21:51:24 -07:00
Austin Tajiri
7cab0e7124 gpu: nvgpu: add ltc.intr.retrigger HAL 
Add an ltc.intr.retrigger HAL for chips that need to retrigger pending
interrupts in the LTC ISR.

Jira NVGPU-9217

Change-Id: I1fe74c2f72afc7cf852cf0d273c7a8f8652a53c9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869902
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:26 -07:00
Austin Tajiri
db22d49239 gpu: nvgpu: add LTC interrupt register HALs 
Add HALs for reading and writing LTC interrupt configuration registers.

Jira NVGPU-9217

Change-Id: I2d3a913ae5e69009d7888495af9b79acb4960ac9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869901
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:20 -07:00
Austin Tajiri
b1ac11e0e0 gpu: nvgpu: add ltc.intr.handle_illegal_compstat HAL 
Add ltc.intr.handle_illegal_compstat to handle the case in which a chip
does not support the ILLEGAL_COMPSTAT LTC interrupt.

Jira NVGPU-9217

Change-Id: I40ddcbda6176ffa36037bd1998af4ec1bed67ec9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869900
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:14 -07:00
Austin Tajiri
3a69b445fc gpu: nvgpu: fix MMU fault register mismatches 
Fix the following MMU register mismatches by using the appropriate HALs
when possible:
 - fb_mmu_fault_status_r
 - fb_mmu_debug_ctrl_r

Jira NVGPU-9217

Change-Id: I3380ac449f20f2ce47b439303b9abd19010e6b26
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869899
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:08 -07:00
Austin Tajiri
f2ce282b7e gpu: nvgpu: add HALs for ECC interrupt handling registers 
Add HALs for reading ECC status, retrieving ECC error info, and clearing
ECC errors. Use these HALs in place of direct register access in
GV11B/GA10B ECC interrupt handlers.

Jira NVGPU-9217

Change-Id: I792f05ede5576b958b678bc5eb8f2b8dc5e7c4d7
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869898
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-04-04 21:42:03 -07:00