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gpu: nvgpu: add LTC interrupt register HALs

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Add HALs for reading and writing LTC interrupt configuration registers.

Jira NVGPU-9217

Change-Id: I2d3a913ae5e69009d7888495af9b79acb4960ac9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869901
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Austin Tajiri
2023-03-13 02:31:14 +00:00
committed by mobile promotions
parent b1ac11e0e0
commit db22d49239
5 changed files with 63 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/hal/init/hal_ga100.c
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@@ -376,6 +376,12 @@ static const struct gops_ltc_intr ga100_ops_ltc_intr = {
.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
.handle_illegal_compstat = ga10b_ltc_intr_handle_illegal_compstat,
#endif
.read_intr1 = ga10b_ltc_intr_read_intr1,
.read_intr2 = ga10b_ltc_intr_read_intr2,
.read_intr3 = ga10b_ltc_intr_read_intr3,
.write_intr1 = ga10b_ltc_intr_write_intr1,
.write_intr2 = ga10b_ltc_intr_write_intr2,
.write_intr3 = ga10b_ltc_intr_write_intr3,
};
static const struct gops_ltc ga100_ops_ltc = {

6
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -350,6 +350,12 @@ static const struct gops_ltc_intr ga10b_ops_ltc_intr = {
.en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
.handle_illegal_compstat = ga10b_ltc_intr_handle_illegal_compstat,
#endif
.read_intr1 = ga10b_ltc_intr_read_intr1,
.read_intr2 = ga10b_ltc_intr_read_intr2,
.read_intr3 = ga10b_ltc_intr_read_intr3,
.write_intr1 = ga10b_ltc_intr_write_intr1,
.write_intr2 = ga10b_ltc_intr_write_intr2,
.write_intr3 = ga10b_ltc_intr_write_intr3,
};
static const struct gops_ltc ga10b_ops_ltc = {

6
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b.h
View File

@@ -40,5 +40,11 @@ void ga10b_ltc_intr_handle_lts_intr3(struct gk20a *g, u32 ltc, u32 slice);
void ga10b_ltc_intr_handle_lts_intr3_extra(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
void ga10b_ltc_intr_handle_illegal_compstat(struct gk20a *g, u32 ltc, u32 slice,
u32 ltc_intr, u32 *reg_value);
u32 ga10b_ltc_intr_read_intr1(struct gk20a *g);
u32 ga10b_ltc_intr_read_intr2(struct gk20a *g);
u32 ga10b_ltc_intr_read_intr3(struct gk20a *g);
void ga10b_ltc_intr_write_intr1(struct gk20a *g, u32 reg_val);
void ga10b_ltc_intr_write_intr2(struct gk20a *g, u32 reg_val);
void ga10b_ltc_intr_write_intr3(struct gk20a *g, u32 reg_val);
#endif /* NVGPU_LTC_INTR_GA10B_H */

48
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_ga10b_fusa.c
View File

@@ -32,12 +32,42 @@
#include <nvgpu/hw/ga10b/hw_ltc_ga10b.h>
u32 ga10b_ltc_intr_read_intr1(struct gk20a *g)
{
return nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
}
u32 ga10b_ltc_intr_read_intr2(struct gk20a *g)
{
return nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
}
u32 ga10b_ltc_intr_read_intr3(struct gk20a *g)
{
return nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
}
void ga10b_ltc_intr_write_intr1(struct gk20a *g, u32 reg_val)
{
nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), reg_val);
}
void ga10b_ltc_intr_write_intr2(struct gk20a *g, u32 reg_val)
{
nvgpu_writel(g, ltc_ltcs_ltss_intr2_r(), reg_val);
}
void ga10b_ltc_intr_write_intr3(struct gk20a *g, u32 reg_val)
{
nvgpu_writel(g, ltc_ltcs_ltss_intr3_r(), reg_val);
}
static void ga10b_ltc_intr1_configure(struct gk20a *g)
{
u32 reg;
/* Enable ltc interrupts indicating illegal activity */
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
reg = g->ops.ltc.intr.read_intr1(g);
/*
* IDLE_ERROR_CBC - flag if cbc gets a request while slcg clock is
@@ -92,10 +122,10 @@ static void ga10b_ltc_intr1_configure(struct gk20a *g)
reg = set_field(reg, ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(),
ltc_ltcs_ltss_intr_en_illegal_compstat_access_enabled_f());
nvgpu_writel(g, ltc_ltcs_ltss_intr_r(), reg);
g->ops.ltc.intr.write_intr1(g, reg);
/* Read back register for write synchronization */
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr_r());
reg = g->ops.ltc.intr.read_intr1(g);
#ifdef CONFIG_NVGPU_NON_FUSA
/* illegal_compstat interrupts can be also controlled through
@@ -114,7 +144,7 @@ static void ga10b_ltc_intr2_configure(struct gk20a *g)
{
u32 reg;
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
reg = g->ops.ltc.intr.read_intr2(g);
/*
* TRDONE_INVALID_TDTAG - The tdtag for a transdone does not match any
@@ -244,10 +274,10 @@ static void ga10b_ltc_intr2_configure(struct gk20a *g)
ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_m(),
ltc_ltcs_ltss_intr2_en_checkedin_unexpected_trdone_enabled_f());
nvgpu_writel(g, ltc_ltcs_ltss_intr2_r(), reg);
g->ops.ltc.intr.write_intr2(g, reg);
/* Read back register for write synchronization */
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr2_r());
reg = g->ops.ltc.intr.read_intr2(g);
}
void ga10b_ltc_intr3_configure_extra(struct gk20a *g, u32 *reg)
@@ -294,7 +324,7 @@ static void ga10b_ltc_intr3_configure(struct gk20a *g)
{
u32 reg;
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
reg = g->ops.ltc.intr.read_intr3(g);
/*
* CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT - RWC/Upgrade to the same 256B
@@ -379,10 +409,10 @@ static void ga10b_ltc_intr3_configure(struct gk20a *g)
g->ops.ltc.intr.ltc_intr3_configure_extra(g, &reg);
}
nvgpu_writel(g, ltc_ltcs_ltss_intr3_r(), reg);
g->ops.ltc.intr.write_intr3(g, reg);
/* Read back register for write synchronization */
reg = nvgpu_readl(g, ltc_ltcs_ltss_intr3_r());
reg = g->ops.ltc.intr.read_intr3(g);
}
void ga10b_ltc_intr_configure(struct gk20a *g)

6
drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
View File

@@ -200,6 +200,12 @@ struct gops_ltc_intr {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
void (*configure)(struct gk20a *g);
u32 (*read_intr1)(struct gk20a *g);
u32 (*read_intr2)(struct gk20a *g);
u32 (*read_intr3)(struct gk20a *g);
void (*write_intr1)(struct gk20a *g, u32 reg_val);
void (*write_intr2)(struct gk20a *g, u32 reg_val);
void (*write_intr3)(struct gk20a *g, u32 reg_val);
#ifdef CONFIG_NVGPU_NON_FUSA
void (*en_illegal_compstat)(struct gk20a *g, bool enable);
void (*handle_illegal_compstat)(struct gk20a *g, u32 ltc, u32 slice,