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10 Commits

Author SHA1 Message Date
Philip Elcan
cf8707e2b3 gpu: nvgpu: mm: add hal to get max page table levels 
Add a HAL API to get the maximum page table levels for the current
hardware.

JIRA NVGPU-3489

Change-Id: I1635ca576f3db461afb8e4e46db1e8912bcfdcd6
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224449
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Scott Long
a139172130 gpu: nvgpu: mm: fix misra 2.7 violation 
Advisory Rule 2.7 states that there should be no unused
parameters in functions.

This patch removes the unused struct gk20a pointer from
the nvgpu_aperture_str() function.

Jira NVGPU-3178

Change-Id: Ied7fed13e44f1083e7477a5d6fb9facafca838de
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2174883
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-08-14 15:17:14 -07:00
Nicolas Benech
9a4ad88f21 gpu: nvgpu: hal: split MM-related HALs based on FUSA 
This patch moves MM HALs that are guaranteed to be functionaly safe
into _fusa.c files. HALs that are not part of FUSA are not compiled
anymore when the safety profile is enabled.

Given a HAL source file:
- it may contain only FUSA code, in that case the source file is
  simply renamed with the _fusa postfix.
- it may contain only non-FUSA code, in that case the file is left
  as-is
- it may contain a mix, in that case the original file will now only
  contain non-FUSA code, and all FUSA code will be moved into a new
  source file with the _fusa postfix.

JIRA NVGPU-3690

Change-Id: I44c604aef2d72252abb7da1c0ef1210d71a0efa7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140895
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-27 01:36:07 -07:00
Sagar Kamble
556ddaf9a3 gpu: nvgpu: add support for removing comptags and cbc from safety build 
Safety build does not support compression. This patch adds support to
compile out compression related changes - comptags, cbc.

JIRA NVGPU-3532

Change-Id: I20e4ca7df46ceec175b903a6a62dff141140e787
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125473
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 10:55:27 -07:00
Philip Elcan
66c79f3bb3 gpu: nvgpu: mm: use u64 for get_mmu_levels() 
Change the big_page_size parameter for the HAL API get_mmu_levels from
u32 to u64. This eliminates a CERT-C INT31 violation in page_table.c for
casting without checking the value.

JIRA NVGPU-3515

Change-Id: If001407666acd21733017f420e615ae6bd6d929c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125026
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-29 12:59:40 -07:00
Thomas Fleury
99bdda5846 gpu: nvgpu: fix MISRA 21.2 violations in nvgpu.hal.mm.gmmu 
Renamed the following functions to fix MISRA 21.2 violations:
- __update_pte -> update_pte
- __update_pte_sparse -> update_pte_sparse

Jira NVGPU-3284

Change-Id: Ic2281254f362ca261ab66562a4160acd3bf7ebc2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 10:58:11 -07:00
Thomas Fleury
56718737d9 gpu: nvgpu: fix MISRA 15.7 violations in nvgpu.hal.mm.gmmu 
Refactored if / else statements in nvgpu.hal.mm.gmmu
to avoid "else if" with no terminating "else" statement.

Jira NVGPU-3284

Change-Id: Id0a5901f6e74ab1b6539f8b907a4e8fdf3c1396c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119616
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 10:58:01 -07:00
Thomas Fleury
8a9d329468 gpu: nvgpu: fix MISRA 10.3 violations in nvgpu.hal.mm.gmmu 
Fixed MISRA 10.3 violations by using explicit casts, and
changing essential types.

Jira NVGPU-3284

Change-Id: If16c09a5100a9437e3e22bc53a81d3d1687d5cb1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119615
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 10:57:52 -07:00
Alex Waterman
6c2c4181ae gpu: nvgpu: Create hal.mm.mm for misc MM HALs 
There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.

Much of this is fairly straightforward copy/paste and updates to the
HAL init files.

The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.

JIRA NVGPU-2042

Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-01 15:06:57 -07:00
Alex Waterman
efbe371fd5 gpu: nvgpu: Create hal/mm/gmmu and move gk20a GMMU code 
Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.

This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.

JIRA NVGPU-2042

Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-23 12:45:54 -07:00