As a part of refactoring, we need to move the volt unit from perf to pmu
as it belongs there and also move the arbitor specific functions under
CLK_ARB as they will be removed from safety build.
This patch does the following
*Move volt struct from perf to pmu
*Move volt setup from pmu_pstate to volt
*Move clk freq related functions into CLK_ARB
NVGPU-4491
NVGPU-4492
Change-Id: I7180cd12bbf91cc4d2e79b6e2d71c16e494c8ff0
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268215
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.
Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.
PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.
Update the doxygen for changed functions.
JIRA NVGPU-4439
Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
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This patch constructs the initial setup for sync unit.
There are three simple tests currently. The first test inits the
environment necessary such as regspace init, hal init. The second
step simply fails the creation of the sync and the last test is meant
as a deinit step.
JIRA NVGPU-913
Change-Id: I1db72d9833c3c4bc3c3903a7d81cce06e9983509
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248493
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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.
For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.
JIRA NVGPU-4336
Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.
Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.
JIRA NVGPU-4336
Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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Currently for every +/-5 degC change in
temperature, PMU internally evaluate VF curve on
temp change and will send VFE callback to NVGPU for
initiating change seq to program voltage and frequency.
This is the only callback we receive on temp change
which we handle in perf unit, and we don't have any
other temp events raised by PMU.
So, deleting the therm event handler.
NVGPU-4360
Change-Id: I3c7279dcf691135c178b6a05766403a935bc7e73
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2241488
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1. Move common.class HAL outside gk20a.h for documentation purpose.
2. Add the new HAL header file to yaml.
3. Add doxygen comments to all the FUSA public defines and HALS.
4. Use @cond...@endcond to skip documentation for NON-FUSA HALs.
JIRA NVGPU-2487
Change-Id: Ib80e8e6e56073fe26a1810fd082c8ec6a115e22d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2232234
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The devinit executes in parallel with PCIE link training
to reduce exit latency. Therefore, all PCIE settings that
normally occur during devinit after the PCIE link is up are
deferred until nvgpu has resumed control.
Bug 2661545
Change-Id: Ifdd4f645b2e1791d93567cc34d6ab0691a25d101
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210625
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226017
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Currently nvgpu queue APIs are in nvgpu_rmos folder
but they can be moved to Posix layer. This change adds
the queue APIs to posix layer and the same will get deleted
from the nvgpu_rmos folder.
JIRA NVGPU-2679
Change-Id: I1d33c9f8eeae5fcb8e628b755e788d0be6310e47
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2229355
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move ptimer unit HALS outside gk20a.h. This is required for
documenting the HALs. We divide the ptimer unit HALs into 3 categories:
1. Private HALs
2. FUSA HALs
3. NON-FUSA HALs
This classification will help focus only on FUSA HALs in design
document and exclude the non-safety related ones from design
document.
Add ptimer HAL header file which contains the HALs exposed by ptimer
unit.
Use @cond...@endcond to skip documentation for NON-FUSA HALs and
private HALs from ptimer unit.
Add doxygen comments for
1. ptimer unit's public HAL used in safety build
a. ptimer.isr
2. ptimer unit's public APIs
a. ptimer_scalingfactor10x()
b. ptimer_scale()
JIRA NVGPU-2503
Change-Id: If5fb00733e122b27826ec36503f175fae172c71b
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219427
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This move is required for documenting the HALs. We divide the
Top unit HALs into 3 categories:
1. Private HALs
2. FUSA HALs
3. NON-FUSA HALs
This classification will help focus only on FUSA HALs in design
document and exclude the non-safety related ones from design
document.
Also, add this HAL header file to yaml.
JIRA NVGPU-2500
Change-Id: I8325b4bb2677cba9be94e15ec2683d1c9e0bc68e
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2215228
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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.
JIRA NVGPU-4144
Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216106
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Separate out common.therm as safe unit since it is being used for
gv11b.
Create new hal.therm_fusa as safe unit since it is needed for gv11b.
Create hal.therm as non-safe unit.
Change-Id: Ife1cd17364d703db5e6be662625286356a8d966e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2212927
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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MISRA rule 17.1 forbids use of stdarg.h features defined for variable
arguments. This patch creates timers.h header for posix and QNX to
change nvgpu_timeout_expired_msg() to macro definition.
Jira NVGPU-4075
Change-Id: I8167f0ff7fdfb74adbbbed9c3021a9df2ad6401b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200885
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MISRA Rule 17.1 forbids use of stdarg.h features which are defined for
variable arguments.
This patch modifies logging macros to use slogf function for QNX builds.
This avoids use of variable argument functions used for formatting log
message.
Jira NVGPU-4075
Change-Id: I5b6bb1107a7e431afaa960003858193a477b2ee6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192016
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Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.
JIRA NVGPU-3853
Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GR tick frequency needs to be set to MAX value for profiler
use cases for gp10b/gv11b/tu104 chips.
Add new HAL g->ops.ptimer.config_gr_tick_freq() that configures GR
tick frequency to MAX value and call this HAL in GPU poweron path.
This support is not needed in safety build, so compile everything
only if CONFIG_NVGPU_DEBUGGER is enabled
Bug 200289214
Change-Id: Id8378540cc67ca0041b56990f8676e3a105403a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195163
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nvgpu_cg_pg_enable|disable functions are non-safe hence compile out
power_features.c. Corresponding functions from cg.c are also not
compiled. for e.g. nvgpu_cg_elcg_enable|disable, nvgpu_cg_blcg-
_mode_enable|disable, nvgpu_cg_slcg_gr_perf_ltc_load_enable|disable,
nvgpu_cg_elcg_set_elcg|blcg|slcg_enabled.
BLCG handling in nvgpu_cg_set_mode is non-safe hence compile it out
as well.
JIRA NVGPU-2175
Change-Id: I9940cc418d84eb30979dd50a2ed4a132473312fe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168957
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