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Author SHA1 Message Date
Richard Zhao
84ddb23633 gpu: nvgpu: move .force_ctx_reload to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Id4e815e9cf78a43156449d0e77e8e331fc906725
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863439
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:56:10 -07:00
Richard Zhao
c8d6a91de6 gpu: nvgpu: update .channel.enable/disable to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ibd94ab8c9f0492bd6d20243525905d637eb8de66
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:56:04 -07:00
Richard Zhao
d9c8d317f0 gpu: nvgpu: update .read_state to use runlist_id and chid 
Moving to use IDs rather than struct makes it reusable on server side.

Jira GVSCI-15770

Change-Id: Ia5e30ebb0e8092b9cdc4c3f3cd524f585fd4b410
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863437
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:58 -07:00
Richard Zhao
2ff110f722 gpu: nvgpu: update .clear to use runlist_id and chid 
- Moving to use IDs rather than struct makes it reusable on server side.
- move channel bind/unbind to use .enable/.clear HALs

Jira GVSCI-15770

Change-Id: I86d4aae2953024e537e32a35fe9cabb1b91cd201
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863436
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:53 -07:00
Richard Zhao
3edae21ca6 gpu: nvgpu: vgpu: add vgpu-next cmds support 
vgpu-next cmds will be used if CONFIG_NVGPU_NEXT is set.

Jira GVSCI-15770

Change-Id: Iddb2c8b5c0ca412c99bfd01fd7d6411d4439131f
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863435
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-13 04:55:47 -07:00
Richard Zhao
7cd377568f gpu: nvgpu: vgpu: init ctx buffers for vf driver 
VF needs to allocate gr ctx buffers on gr init, since VF will manage the
gr ctx.

Jira GVSCI-15769

Change-Id: Ifd09e6b09306c0fd36bddc60caa3d0d56f2b29cb
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863434
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-13 04:55:35 -07:00
Rajesh Devaraj
e5c5fee01e gpu: nvgpu: skip falcon sw init for pmu 
Perform falcon sw init for PMU only if it is supported in the platform.

JIRA NVGPU-9283

Change-Id: I697e389a7cd812c7cb941eac010549f541074bb4
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2848436
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-03-12 19:47:32 -07:00
Austin Tajiri
6196d3f382 gpu: nvgpu: ga10b: fix missing gr registers 
Add the following missing GR registers/fields for GA10B:
 - gr_exception_fe_m
 - gr_exception_memfmt_m
 - gr_exception_pd_m
 - gr_exception_scc_m
 - gr_exception_ds_m
 - gr_exception_ssync_m
 - gr_exception_mme_m
 - gr_exception_sked_m
 - gr_fe_hww_esr_info_r
 - gr_mme_hww_esr_info_r
 - gr_sked_hww_esr_r
 - gr_sked_hww_esr_reset_active_f

Jira NVGPU-9217

Change-Id: I7bffb0f4e605ee09e75c7f550cece6779b71a80e
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2866781
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:16:01 -07:00
Richard Zhao
d118c95803 gpu: nvgpu: vgpu/linux: add ptimer_src_freq needed by construct runlist 
Jira GVSCI-15773

Change-Id: I251c4e348e0019cbf43db103ef8700ca7bb49172
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863433
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Austin Tajiri <atajiri@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:14:15 -07:00
Richard Zhao
a23e574de0 gpu: nvgpu: vf: init syncpt mem 
Since gmmu map is moved to VF, the syncpt mem map is also on VF clients.

Jira GVSCI-15733

Change-Id: Iaf68070da860616f5301a822ce98581b8a1a6629
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863445
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:52 -07:00
Richard Zhao
a7d358f773 gpu: nvgpu: vf: init gmmu related structure 
vf driver implements gmmu map/unmap on client side.

- adds helper function to check whether nvgpu device is vf or legacy
vgpu.
- inits pd_cache struct for vf
- inits platform->phys_addr for ipa2pa

Jira GVSCI-15733

Change-Id: I46c84f0acdd167b9c4bdcec2f1c25f3acd6a0f71
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863430
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:47 -07:00
Richard Zhao
de0e1be1ed gpu: nvgpu: add g->func_regs 
rework nvgpu_func_* io accessors to use g->func_regs rather than use
g->regs. g->regs is invalid for VF.

Jira GVSCI-15732

Change-Id: I71e788ff135c5a286b273c151e1bd0a88e9d61e2
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863429
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-12 08:13:41 -07:00
Ashish Mhetre
d50889585e gpu: nvgpu: os: linux: Zero out dma_buf_map struct 
UBSAN is reporting "invalid-load include/linux/dma-buf-map.h".
This is because non-boolean value loaded to bool variable is_iomem
of dma_buf_map struct. Zeroing out this struct at declaration time
make sure that there is no garbage value which will be non-boolean.

Bug 3994163

Change-Id: Ib18448e8fc09cbcb25c3eeb3e5deec805f6ed008
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869262
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-11 19:21:31 -08:00
Richard Zhao
8c97129c12 gpu: nvgpu: enable vgpu for oot kernel 
Jira GVSCI-16046

Change-Id: I17b690a842bfe76243cac64c2274e049f99095b1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2866153
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Manish Bhardwaj <mbhardwaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-08 18:44:23 -08:00
Ramalingam C
14cb86727c gpu: nvgpu: Modify device node path for iGPU-PCIe 
Create device nodes for iGPU-PCIe at /dev/nvgpu/igpu-XXXX:XX:XX.X/
This helps to identify the GPU type and its location at PCIe bus.

Example dev node entry:
	/dev/nvgpu/igpu-0000:01:00.0/power

JIRA NVGPU-9451

Change-Id: If66714467a989370c85c1e81d6e6c0c02ce0e6f4
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2847618
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-08 18:35:29 -08:00
Kishan
a765a76c81 gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes. 
Added new gr_config member to hold TPC physical id map.
Updated ecc stats structures to hold physical gpc,tpc
numbers. Previously logical id's were exposed via ecc
sysfs nodes.
Consumers of ecc sysfs nodes refer tpc_fs_mask which is
physical gpc/tpc layout whereas ecc sysfs nodes were updated
with logical gpc/tpc layout. This change ensures that both
use the same framework.

JIRA NVGPU-9607
Bug 3950378

Change-Id: I1f91956dd027ffdc12042dd33dc491a3ce1e1ff6
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2866264
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-08 06:32:00 -08:00
Divya
6d65e58fd2 gpu: nvgpu fix coverity issue in therm/cg unit 
Add NULL check for ELCG and BLCG HALs based on cgmode
to avoid coverity issue: CWE-476: NULL Pointer Dereference

Bug 3952896

Change-Id: I3ee717645bbecaafddb5d485f57550e213bf762b
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864656
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-08 06:30:51 -08:00
Sagar Kamble
2acfb55780 gpu: nvgpu: fix tex rd coalesce disable logic 
NETLIST_REGIONID_SW_CTX_LOAD writes update gr_gpcs_tpcs_tex_m_dbg2_r to
default value that keeps rd coalesce enabled for LG & SU.

Disable rd coalesce for tex, lg and su after NETLIST_REGIONID_SW_CTX_LOAD
writes during gr init and golden ctx init for it to take effect.

For gr sw method handling, don't update the tex rd coalesce on interrupt
with offset *_SET_RD_COALESCE as we want to keep rd coalescing disabled.

Bug 3881919

Change-Id: Ie7e6616d48f84547ce3380bfa395910b7995c05b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857141
(cherry picked from commit b2c8827c65)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859538
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-07 22:46:44 -08:00
Richard Zhao
3af0fe510e gpu: nvgpu: add nvgpu-next to Makefile.sources 
It's for gpu server or qnx could use nvgpu-next. It only includes
nvgpu-next Makefile.sources. The user should decide whether to enable
CONFIG_NVGPU_NEXT.

Jira GVSCI-15646

Change-Id: Ic70a4de668dd5e05a68fc57755a1f0aed9548ca5
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858883
Reviewed-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
 2023-03-05 04:09:43 -08:00
srajum
4ef14a13ff gpu: nvgpu: pmu use PWRCLK at fixed rate 204MHZ 
- On T234, Getting clock by calling clk.get_rate with CTRL_CLK_DOMAIN_PWRCLK
  domian which eventually pass clk index 1U which access TEGRA234_CLK_GPC0CLK.
- But GPC0 is floor-swept which returns makes clk.get_rate API fail
  (failed to query source clock).

Bug 3998230

Change-Id: I0a674b1856daf2b899827a7aafe0fc4185dd9964
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2862998
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-03-01 10:26:28 -08:00
V M S Seeta Rama Raju Mudundi
ab46ee3335 Revert "gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes." 
This reverts commit 2cc098eae7.

Reason for revert: intermittent boot failures on drv-orin-f1 and 
frspr-f1 on both AV+L and AV+Q.

Bug 3998230

Change-Id: I230ba7ba469fde3f470dab7538cc757c99360d99
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863208
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-25 11:16:12 -08:00
Sagar Kamble
a4eca46b4b gpu: nvgpu: Enable compression for k6.1 
dmabuf internals that nvgpu relies upon for storing meta-data for
compressible buffers changed in k6.2. Enable it for k6.1.

Bug 3844023

Change-Id: Ief661b3739e987dc8f2fe13bb0efb02fa78dbacd
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2861335
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-24 04:06:02 -08:00
Kishan
2cc098eae7 gpu:nvgpu: Expose physical gpc,tpc layout for ecc sysfs nodes. 
Added new gr_config member to hold TPC physical id map.
Updated ecc stats structures to hold physical gpc,tpc
numbers. Previously logical id's were exposed via ecc
sysfs nodes.
Consumers of ecc sysfs nodes refer tpc_fs_mask which is
physical gpc/tpc layout whereas ecc sysfs nodes were updated
with logical gpc/tpc layout. This change ensures that both
use the same framework.

JIRA NVGPU-9607
Bug 3950378

Change-Id: Iac99951fc3aa9dde02e833109f32aa5bb37ea15f
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2855032
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-22 00:42:23 -08:00
Alex Waterman
03533066aa gpu: nvgpu: Disable compression for k6.1+ 
dmabuf internals that nvgpu relies upon for storing meta-data for
compressible buffers changed in k6.1. For now, disable compression
on all k6.1+ kernels.

Additionally, fix numerous compilation issues due to the bit rotted
compression config. All normal Tegra products support compression
and thus have this config enabled. Over the last several years
compression dependent code crept in that wasn't protected under the
compression config.

Bug 3844023

Change-Id: Ie5b9b5a2bcf1a763806c087af99203d62d0cb6e0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820846
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Tested-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-21 03:36:00 -08:00
Rajesh Devaraj
b754a2f0cf gpu: nvgpu: add and update falcon_dump_stats 
Add dump_falcon_info to avoid the duplication of entire
falcon_dump_stats function for new chips.

JIRA NVGPU-9216

Change-Id: I0a0c7b4655c625222a8fd3538d9e855568616e3a
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-18 14:07:09 -08:00
Ramalingam C
d6be1bdcfe gpu: nvgpu: add is_pci_gpu 
Add a flag is_pci_gpu into platform data and gk20a, to support
igpu as pcie device.

JIRA NVGPU-9348

Change-Id: Iff1439ebb834b1673cb75ea26ca1e7626e1af0d5
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2835340
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-18 02:29:35 -08:00
Rajesh Devaraj
4bbc766454 gpu: nvgpu: add intr_0_pbcrc_pending gops for pbdma 
Add intr_0_pbcrc_pending hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ia08ce7761ac5b9a1af1166efbc1ecba97b54fc87
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857919
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:31:23 -08:00
Rajesh Devaraj
5aae7df6cd gpu: nvgpu: add reset_method pbdma gops 
Add reset_method hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: Ice9c3f6aea33a8dadae5841f1a6387303495ba98
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-17 07:26:24 -08:00
Richard Zhao
30727e8a93 gpu: nvgpu: remove golden_ctx_init_ch 
golden_ctx_init_ch is not used anmore because golden image creation has
been separated from channel/tsg.

Jira GVSCI-15771

Change-Id: I2af49717f8debbdb389ac64339e6ea7f84507a4e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2857563
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-16 00:00:59 -08:00
Richard Zhao
1e95ebef53 gpu: nvgpu: separate golden image creation from tsg/ch 
Golden image creation asks FECS to bind inst_block directly. It does not
need any setup on esched. Separating it from tsg/ch makes it for
flexible.

Jira GVSCI-15771

Change-Id: Id446371eb60b9520a7a284120a72c13d2215f4ea
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-16 00:00:53 -08:00
Rajesh Devaraj
cc17f80896 gpu: nvgpu: add gops to init pce2lce and grce configs 
This patch adds the following gops for CE unit:
- init_pce2lce_configs
- init_grce_configs

JIRA NVGPU-9329

Change-Id: I6e067b1f5066ccd71c4b287fa564a77afe4a25a5
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2856498
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-13 05:42:22 -08:00
Rajesh Devaraj
2e73de831f gpu: nvgpu: add is_sw_method_subch pbdma gops 
Add is_sw_method_subch hal to avoid duplication of the entire function
for new chips.

JIRA NVGPU-9325

Change-Id: If18a2d510f77e269cb00dde609ec1c5941622858
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2855046
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prathap Kumar Valsan <prathapk@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-13 05:40:54 -08:00
Rajesh Devaraj
356812d2c4 gpu: nvgpu: update debug print in rpc recieve 
To aid debugging in the RPC receive path, this patch updates debug
prints to include the received physical address and nvgpu mem address.

JIRA NVGPU-9283

Change-Id: I71917c1ec6594ae57f836df3968c10ce4b1d1bf3
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854022
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-07 19:07:36 -08:00
Rajesh Devaraj
e3e80f8d26 gpu: nvgpu: add check related to pmu_support 
This patch performs the dereferncing of PMU from GPU driver struct only
when PMU is supported.

JIRA NVGPU-9283

Change-Id: I9a589cd999ff726220168cf108c7e419a5f52038
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2854013
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-07 19:07:30 -08:00
prsethi
5d2f56f89f gpu:nvgpu: fix nvs queue ctrl synchronization 
Change fixes the placement of the queue_lock for better synchronization.

Bug 3884011

Change-Id: Ida350eb4d9b922680aa12346ddcf31fd9c53858b
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2850130
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-02-02 10:16:42 -08:00
rmylavarapu
e233ea5836 gpu: nvgpu: SWUD-lite updates for pmu unit. 
This is updating the pmu unit doxygen as per new guidlines.

Jira NVGPU-6976

Change-Id: Idfe43f32f457f0839e8bc5ad93e32fe7565d90b2
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-31 19:28:15 -08:00
Rajesh Devaraj
73679f1ec8 gpu: nvgpu: update enable_fifo_interrupts 
To reuse enable_fifo_interrupts API in future chips, this patch renames
it as ga10b_fifo_enable_intr and adds it to FIFO specific header file.

JIRA NVGPU-9325

Change-Id: I9f313e417281d5861f568bd41593c5135d9c77a9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2848816
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-31 04:19:57 -08:00
rmylavarapu
de190c8979 gpu: nvgpu: fixing unbalanced parentheses 
NVGPU-9297

Change-Id: I4cee2cdbdd37c2369c2320e2f3e5b46c9986a4d5
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2849502
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-27 15:55:29 -08:00
Divya
120f9e40a3 gpu: nvgpu: Add NULL checks for therm HALs 
Add NULL checks for therm HALs

JIRA NVGPU-9495

Change-Id: If4fd1166c11070a978546e701157d2a217008e39
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844938
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: Rajesh Devaraj <rdevaraj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-27 03:05:25 -08:00
rmylavarapu
0c1fc6bcde gpu: nvgpu: gsp sched: enable scheduler for embedded-linux 
NV_BUILD_CONFIGURATION_VARIANT_IS_EMBEDDED is not enabled for embedded
linux and a precise check for embedded-linux should be made for enabling
gsp scheduler on linux platforms.

NVGPU-9297

Change-Id: I2a8fc30670a9a751ecdc051e4f8ca5db8c798595
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2836359
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-25 20:09:58 -08:00
Rajesh Devaraj
77841cc9bb gpu: nvgpu: update pbdma_acquire intr handling 
To reduce duplication of pbdma_handle_intr_0_legacy to new chips, this
patch makes handle_intr_0_acquire as a HAL.

JIRA NVGPU-9325

Change-Id: I225318d45078367d09fc114202d9aeb0f1be374b
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2844872
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-24 03:38:01 -08:00
Austin Tajiri
6fffdddb7a gpu: nvgpu: add priv_ring.intr_retrigger HAL 
Add a priv_ring.intr_retrigger HAL for chips that need to
retrigger pending interrupts in the PRIV_RING ISR.

Jira NVGPU-9217

Change-Id: I976f26a39d148a0ce1ad54b53d982dc0af58197b
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839756
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:51:54 -08:00
Austin Tajiri
976b4efe64 gpu: nvgpu: add gops_gin HAL 
Add a gops_gin struct for handling chip-specific GIN functionality. For
now, it only has the get_intr_ctrl_msg HAL. Each per-unit INTR_CTRL
register holds an opaque 32-bit value that determines how an interrupt
is routed. The layout of this value is determined by GIN. This HAL
allows units to ask GIN how it should program their INTR_CTRL registers.

Jira NVGPU-9217

Change-Id: I18f86e09701634bdb39db6b6e4728cd3595caa02
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839755
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:51:47 -08:00
Rajesh Devaraj
4bb32e33e7 gpu: nvgpu: update pbdma_dump_intr_0 as an hal 
To reduce the duplication of HALs to new chips, this makes pbdma
dump_intr_0 as an HAL.

JIRA NVGPU-9325
JIRA NVGPU-9064

Change-Id: I737146068cb144165bae8666c04f876aed20a89c
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2847566
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:39:36 -08:00
Bharat Nihalani
4c77431eaf gpu: nvgpu: fix return value check 
Function nvgpu_clk_arb_debugfs_init returns 0 on success,
and -ENOMEM on failure.

Current implementation checks return value incorrectly.
Fix the return value check for this function.

Bug 3752450

Change-Id: I073411f167d8378506f269b43c765ef4f406bce3
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2846931
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-23 22:37:58 -08:00
Rajesh Devaraj
7ad50fee7c gpu: nvgpu: add new device types 
This patch adds macros for new device types based on the device
information table. Specifically, it adds the device type IDs for the
following engines:

- SEC
- NVENC
- NVDEC
- NVJPG
- OFA

Further, the max dev types has been updated as 57 in the device info
table. To support his, the corresponding macro has been updated as 58.

JIRA NVGPU-9501

Change-Id: I23f17c91da8a6063457c27763a62b1a08beeed0d
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2846203
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-21 16:52:39 -08:00
Rajesh Devaraj
afb971b66e gpu: nvgpu: update report_pbdma_error as hal 
To reduce the duplication pbdma_handle_intr_0 API to new chips, this
patch converts report_pbdma_error as a HAL.

JIRA NVGPU-9325

Change-Id: Ifcb0838037c750070c26343e008a176b26eebf16
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2845088
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-20 03:40:17 -08:00
srajum
6d7ace12dc nvgpu: Fix CERT-C defects 
Fix following CERT-C defects

- CID 631480
- CID 494546

Bug 3745813

Change-Id: I33ad7d044cc18219a117811b960dae26cf744983
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2834699
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-20 03:35:49 -08:00
Vince Hsu
db637cd585 gpu: nvgpu: unit: mm: fix compilation error with GCC 11.2 
The maybe-uninitialized in GCC 11.2 reports the error below:

error: 'l' may be used uninitialized [-Werror=maybe-uninitialized]

Fix it by explicitly initialize the struct as zero.

Bug 200730650

Change-Id: I5cc279e80fb8d2eb7839888da94a4336588f0324
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2770727
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-19 14:36:16 -08:00
Austin Tajiri
26e325aaf2 gpu: nvgpu: fix ga10b vgpu dma_mask 
Set ga10b's vgpu dma_mask to DMA_BIT_MASK(39). The vGPU can access the
full physical address space.

Bug 3918582

Change-Id: I527f1e569055c7b4eccddb4ef9bdbef6ee6e2bb5
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2841221
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2023-01-17 16:16:50 -08:00