Implement the 5-level Pascal page table format. It is enabled
only for simulation.
Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/682114
Add a missing bitmask for clearing existing bits before setting a new
value, and shift the value the correct amount. Also format register
needs to be rounded down.
Bug 200087330
Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/726265
Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Remove the requirement that srcdir is called kernel.
Change-Id: I9379ef530ac34009bd0461a29d65d6d707bc8014
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/728153
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Program steady state CB size to be the HW default.
Bug 1626065
Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/725106
Program a constant stream id 31 to LTC.
Bug 1610019
Change-Id: I9b5fb794b5ea8da0fba67a2376126d89e056f955
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/724348
Reviewed-by: Automatic_Commit_Validation_User
Add platform specific gp10b_mm_iova_addr() to get
iova/phys address for gp10b
If SMMU is not enabled and IO coherence flag is set,
set 34th bit in the physical address and return the
physical address
If SMMU is enabled, return the iova address
Bug 1605653
Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713106
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Do not clear compbit store size if max size is zero. It's already
zero at this point.
Change-Id: I70d99cfe459fae27d8c1be4aa569ac0717a454d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/720599
Move the fifo engine activity disabling and wait-for-idle from the
lowest-level functions higher, into the ioctl path of zbc operations, so
that the sw initialization path wouldn't call them. During the init
path, the disable isn't necessary, and the code path could result in a
deadlock in the fifo runlist mutex.
Change-Id: I56e73204e288331165358fc9856390f1eb724488
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/715196
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Use gp10b version of get_physical_addr_bits.
Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/714402
ce interrupts use different register mapping
and format from gk20a and gm20b.
Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/681646
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GPFIFO class was set to Maxwell class number. Also implement the
PBDMA signature HAL.
Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/672921
Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE
during t18x ltc init and store it for use in CDE code.
Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/673150
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Define compression page size for gp10b to be 64k. We also need to
copy some LTC initialization code from gm20b to gp10b.
Change-Id: I0235c32cdb1486a23d33eb98ebbc79c97a3c32d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677837
Remove hard coded NETB for gp10b. This enables cycling through
available firmware files.
Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/676557
Reviewed-by: Peng Du <pdu@nvidia.com>
GVS: Gerrit_Virtual_Submit
L2 size is expressed in kB, so add a multiplier.
Bug 1592495
Change-Id: I4c10034cd21bf874c84c96f1adc25261b195063d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/671704
