Commit Graph

32 Commits

Author SHA1 Message Date
Vinod G
6110bcf586 gpu: nvgpu: Fix MISRA 17.7 errors in gr.intr unit
Fix MISRA 17.7 errors in gr.intr unit
misra_c_2012_rule_17_7_violation: The return value of a non-void
function is unused.

Jira NVGPU-3621

Change-Id: I7b03b8165a628decce66bf886625fe001db76a01
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134530
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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2019-06-12 20:56:57 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
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2019-06-11 09:46:24 -07:00
Vinod G
9b163a0611 gpu: nvgpu: Fix CERT INT30-C errors in gr.intr unit
Fix CERT INT30-C errors in gr.intr unit.
Use safe_ops functions nvgpu_safe_mult_u32 and
nvgpu_safe_cast_u32_to_s32 for multiplication and casting operations.

Jira NVGPU-3412

Change-Id: Ief3d1fe39ace9ba49eb839c823179ef82bacd85f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129768
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2019-06-03 16:47:10 -07:00
Deepak Nibade
e40994c884 gpu: nvgpu: add NVGPU_DEBUGGER flag for SM exception handling
Trap handling and SM preprocessing is not needed in safety build i.e.
when NVGPU_DEBUGGER is false

Add NVGPU_DEBUGGER flag for all unsafe processing.

In safety build we only report the SM exceptions and return error
so that recovery is triggered

Also add flag for gr_intr_post_bpt_events() since event handling
is not needed in safety build

Jira NVGPU-3506

Change-Id: I660930fdb185b82c0adb612decbfd3d014ce2524
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127754
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2019-06-03 04:15:32 -07:00
Deepak Nibade
0908547ad2 gpu: nvgpu: move some interrupt hals to hal.gr.intr unit
Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below

g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()

Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit

All of above functions and hals will be needed in safety build

Jira NVGPU-3506

Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
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2019-06-03 04:15:23 -07:00
Seema Khowala
1e7405a5dc gpu: nvgpu: Add NVGPU_FEATURE_CHANNEL_TSG_CONTROL compiler flag
This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id

JIRA NVGPU-3516

Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
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2019-05-31 16:55:43 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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2019-05-30 02:18:05 -07:00
Vinod G
cd02e4d70f gpu: nvgpu: Fix CERT INT30-C errors in gr intr unit
Fix CERT INT30-C error in gr interrupt units

cert_violation: Unsigned integer operation may wrap.

Use nvgpu_safe_ops macros for addition and subtraction.

Jira NVGPU-3412

Change-Id: Id2d936e77959005616faf069aff6701789342456
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122474
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2019-05-21 15:15:59 -07:00
Debarshi Dutta
4c30bd599f gpu: nvgpu: rename tsg_gk20a*/gk20a_tsg* functions.
rename the functions with the prefixes tsg_gk20a*/gk20a_tsg*
to nvgpu_tsg_*

Jira NVGPU-3248

Change-Id: I9f5f601040d994cd7798fe76813cc86c8df126dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120165
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2019-05-17 01:49:27 -07:00
Vinod G
5c60645cfa gpu: nvgpu: gr_priv header include cleanup
Add more apis in gr_utils for accessing variables within gr struct.
This helps to avoid including gr_priv.h outside gr files and
derefencing gr struct.

Jira NVGPU-3218

Change-Id: I6f24cc302f10aa1da14a981d80c400a027c9a115
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115930
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2019-05-10 20:15:36 -07:00
Seema Khowala
671f1c8a36 gpu: nvgpu: channel MISRA fix for Rule 21.2
Rename
_gk20a_channel_get -> nvgpu_channel_get__func
gk20a_channel_get -> nvgpu_channel_get
_gk20a_channel_put -> nvgpu_channel_put__func
gk20a_channel_put -> nvgpu_channel_put
trace_gk20a_channel_get -> trace_nvgpu_channel_get
trace_gk20a_channel_put -> trace_nvgpu_channel_put

JIRA NVGPU-3388

Change-Id: I4e37adddbb5ce14aa18132722719ca2f73f1ba52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114118
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2019-05-09 04:39:34 -07:00
Seema Khowala
26d13b3b6b gpu: nvgpu: channel MISRA fix for Rule 21.2
Rename functions starting with '_' and '__'.
__gk20a_channel_kill -> nvgpu_channel_kill
_gk20a_channel_from_id -> nvgpu_channel_from_id__func
gk20a_channel_from_id -> nvgpu_channel_from_id

JIRA NVGPU-3388

Change-Id: I3b5f63bf214c5c5e49bc84ba8ef79bd49831c56e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114037
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2019-05-09 04:39:08 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
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2019-05-06 02:56:53 -07:00
Seema Khowala
cfb4ff0bfb gpu: nvgpu: rename struct fifo_gk20a
Rename
struct fifo_gk20a -> nvgpu_fifo

JIRA NVGPU-2012

Change-Id: Ifb5854592c88894ecd830da092ada27c7f05380d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109625
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2019-05-03 16:25:43 -07:00
Seema Khowala
39070c653f gpu: nvgpu: move FIFO_INVAL_* out of fifo_gk20a.h
Move and rename
FIFO_INVAL_ENGINE_ID -> NVGPU_INVALID_ENG_ID
FIFO_INVAL_TSG_ID -> NVGPU_INVALID_TSG_ID
FIFO_INVAL_RUNLIST_ID -> NVGPU_INVALID_RUNLIST_ID
FIFO_INVAL_SYNCPT_ID -> NVGPU_INVALID_SYNCPT_ID
FIFO_INVAL_CHANNEL_ID -> NVGPU_INVALID_CHANNEL_ID

JIRA NVGPU-2012

Change-Id: Ic4cc16ece64d85e22f16e4d28dcfd0c187bb65f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109011
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2019-05-02 23:40:26 -07:00
Vinod G
83f873c95d gpu: nvgpu: MISRA fixes in gr_intr file
Fix one violation for MISRA Rule-13.5
 - Expression after || has persistent side effect
Fix two violation for MISRA Rule-17.7
- Return value is unused

Jira NVGPU-3227

Change-Id: I29127914ffcf2b075c4ac515b3a998f98c779556
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109778
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2019-05-02 18:15:59 -07:00
Seshendra Gadagottu
57be9a09fd gpu: nvgpu: remove circular dependency between gr and fifo
channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.

Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);

JIRA NVGPU-3214

Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
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2019-05-01 20:36:30 -07:00
Vinod G
a965ced5e5 gpu: nvgpu: create gr_intr private header
Move data structs from gr_intr.h to gr_intr_priv.h

Jira NVGPU-3230

Change-Id: I471fb7511cc85fc8551311103aef17fb1a9bec2b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107719
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2019-04-30 18:24:51 -07:00
Deepak Nibade
11110465df gpu: nvgpu: create common.cyclestats unit
Separate out cyclestats handling code into separate unit
common.cyclestats

This unit now exposes new API nvgpu_cyclestats_exec() to perform
cyclestats operation. Call this API from common.gr.intr unit

Extract out all the private data structures from gk20a.h to
cyclestats_priv.h

Rename struct gk20a_cyclestate_buffer_elem to
nvgpu_cyclestate_buffer_elem

Jira NVGPU-1103

Change-Id: Id362675228fe23d03d6d277ff320bcc1066c3c64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104202
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2019-04-25 07:57:05 -07:00
Vinod G
3bbbba8baa gpu: nvgpu: move handle_fecs_error to hal.gr.intr unit
Move gr_gk20a_handle_fecs_error from gr_gk20a.c to
nvgpu_gr_intr_handle_fecs_error in common.gr.intr unit

Move gr_gp10b_handle_fecs_error and gr_gv11b_handle_fecs_error
to hal.gr.intr unit

JIRA NVGPU-3016

Change-Id: I5b7c48ebfd7b13f497980c4d0b64d718649154bd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103741
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2019-04-24 01:29:03 -07:00
Vinod G
490ea365d2 gpu: nvgpu: move handle_sm_exception to gr.intr
Move gr_gp10b_handle_sm_exception from gr_gp10b to
gp10b_gr_intr_handle_sm_exception in hal.gr.intr unit

Move gr_gk20a_handle_sm_exception from gr_gk20a to
nvgpu_gr_intr_handle_sm_exception in common.gr.intr

Move nvgpu_report_gr_sm_exception to common.gr.intr

JIRA NVGPU-3016

Change-Id: I545ddca052122f87685f35f515831841a246dab3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103736
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2019-04-24 01:28:47 -07:00
Vinod G
9a26daf109 gpu: nvgpu: Move handle_sw_method hal to hal.gr.intr unit
Move handle_sw_method hal from gr to gr.intr unit.
Remove gv11b code set_go_idle_timeout, set_coalesce_buffer_size,
use thos function in gp10b code.

NVGPU JIRA-3016

Change-Id: I09ca4070c284fa3a3be28f46a5c584b02b79b7ab
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103059
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2019-04-23 15:44:32 -07:00
Vinod G
dc82262b99 gpu: nvgpu: Add gr_priv header file
Move nvgpu_gr structure to private file gr_priv.h
Include the private file where gr variables are used.

JIRA NVGPU-3132
JIRA NVGPU-3079

Change-Id: Ib26ca5c5cb25fd8dd013a7c643278efc34aa55d4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098021
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2019-04-22 03:15:09 -07:00
Vinod G
8880c82111 gpu: nvgpu: move gk20a_gr_isr to hal
Move gk20a_gr_isr function to stall_isr hal in gr.intr unit.
Move all static functions accessed in gk20a_gr_isr function
to gr_intr file from gr_gk20a file.

Update mc hal functions to use g->ops.gr.intr.stall_isr

JIRA NVGPU-1891
JIRA NVGPU-3016

Change-Id: If379348eef863b8d794a726b98e190ebe8585cb2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100670
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2019-04-20 13:44:02 -07:00
Vinod G
556e139077 gpu: nvgpu: Cleanup for gr_gk20a header
Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.

Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c

Call gr free before the gk20a free call in nvgpu_free_gk20a.

Rename struct gr_gk20a to struct nvgpu_gr

JIRA NVGPU-3132

Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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2019-04-19 00:04:00 -07:00
Vinod G
3d2942e412 gpu: nvgpu: move nvgpu_report_gr_exception to common.gr.intr
Move the nvgpu_report_gr_exception call from gr_gk20a to
gr_intr.c as nvgpu_gr_intr_report_exception

Move local function gk20a_gr_get_channel_from_ctx to gr_intr.c
as nvgpu_gr_intr_get_channel_from_ctx

JIRA NVGPU-1891

Change-Id: I21521ad50989582d8f166a98a21ea3b1dcd3bbff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098229
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2019-04-16 22:35:15 -07:00
Philip Elcan
e3f5e6c271 gpu: nvgpu: gr: fix MISRA 10.3 violations
MISRA Rule 10.3 prohibits assigning objects of different essential or
narrower type. This fixes MISRA 10.3 violations in the gr unit.

JIRA NVGPU-3115

Change-Id: I9817d74eb927f6e52a13d31114e2c579fd65dd32
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094443
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2019-04-15 10:55:57 -07:00
Thomas Fleury
9121f84e67 gpu: nvgpu: move post_event_id from fifo to tsg
Moved the following HAL from fifo to tsg:
- tsg.post_event_id

Implemented as
- nvgpu_tsg_post_event_id

Jira NVGPU-2979

Change-Id: I074233aaf96b33d011b50b1465ea5d76e0a43689
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087186
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2019-04-10 10:36:44 -07:00
Vinod G
3d328ac98e gpu: nvgpu: move gk20a_gr_handle_gpc_exception to common.gr.intr
Move the gk20a_gr_handle_gpc_exception function from gr_gk20a.c
to gr_intr.c as nvpu_gr_intr_handle_gpc_exception.

Move static function gk20a_gr_handle_tpc_exception to
gr_intr.c as gr_intr_handle_tpc_exception

JIRA NVGPU-3016

Change-Id: I42862b00d1946e029673d8f95e0262a44244a87a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090405
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2019-04-07 20:10:05 -07:00
Vinod G
3fa094c646 gpu: nvgpu: move gr_gk20a_isr_data struct to gr_intr.h
Move gr_gk20a_isr_data struct from gr_gk20a.h to
gr_intr.h as nvgpu_gr_isr_data struct.

Update all files that uses the gr_gk20a_isr_data to
nvgpu_gr_isr_data.

JIRA NVGPU-3016

Change-Id: If0ca10a2bbd34f21f430a882403fc7c8a42ec936
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089257
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2019-04-05 08:35:08 -07:00
Vinod G
de93ad0d03 gpu: nvgpu: move handle_semaphore_pending to hal.gr.intr
Move handle_semaphore_pending to hal.gr.intr
gr_gk20a_handle_semaphore_pending function is moved from
gr_gk20a.c to common.gr.intr as nvgpu_gr_handle_semaphore_pending

JIRA NVGPU-3016
JIRA NVGPU-1891

Change-Id: Id731bb4169de9dcfff012e401165ad5a7f43bffa
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089173
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2019-04-05 08:34:38 -07:00
Vinod G
b2caba06f0 gpu: nvgpu: move handle_notify_pending hal to hal.gr.intr
Move handle_notify_pending hal to hal.gr.intr

Move gk20a_gr_handle_notify_pending code from gr_gk20a.c to
common.gr.intr as nvgpu_gr_intr_handle_notify_pending function.

JIRA NVGPU-1891
JIRA NVGPU-3016

Change-Id: Ib3284a83253b03e5708674fce683331ee20b8213
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089172
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-04-05 08:34:23 -07:00