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2 Commits

Author SHA1 Message Date
Philip Elcan
75e4e7c9bc gpu: nvgpu: clk: address MISRA 10.3 violations 
This fixes a number of miscellaneous MISRA 10.3 violations in
common/pmu/clk/ for assignment of objects of different size or essential
type.

JIRA NVGPU-1008

Change-Id: If93aa9fc4f0f49ea678e39111f323ef4d53f5ec5
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008771
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-02-01 13:45:22 -08:00
Terje Bergstrom
dce78f7332 gpu: nvgpu: Move PMU code to common/pmu 
Move code interfacing with PMU tasks to common/pmu.

JIRA NVGPU-961

Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950991
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-01-10 20:09:55 -08:00