rmylavarapu
75f9486b82
gpu: nvgpu: Debugfs for S_param
...
Changes:
1) Added nvgpu_s_param_init_debugfs for creating debugfs interface.
2) Command for S_param value:
cat /sys/kernel/debug/gpu_pci/s_param
3) vfe_var_boardobj_grp_get_status is implemented.
Jira NVGPU-1736
Change-Id: Icbcf39e47777fe969ae2592b58a3103a21011a87
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/1989334
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2019-02-11 20:55:07 -08:00
Philip Elcan
0298551613
gpu: nvgpu: perf: update type for size param
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Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.
JIRA NVGPU-1008
Change-Id: I83676ba8c7f91be610da5e83d15dbecdf767925e
Signed-off-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2011435
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2019-02-11 14:04:28 -08:00
Mahantesh Kumbar
56d14ac403
gpu: nvgpu: Fetch perf change sequence script offset from SSMD
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Fetch perf change sequence script offset from SSMD using member
NV_PMU_SUPER_SURFACE_MEMBER_CHANGE_SEQ_GRP
JIRA - NVGPU-1874
Change-Id: If2f19ee10d30552934052b9212947e408d4e7057
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2000861
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2019-02-07 04:15:34 -08:00
Mahantesh Kumbar
9dda177510
gpu: nvgpu: use common BOARDOBJGRP SET/GET_STATUS construct
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Currently there are multiple BOARDOBJGRP SET/GET_STATUS construct
added to support for 3.5 pstate, _pack boardobjs & to fetch respective
offset/size of boardobjs from PMU super surface.
With super surface member descriptor(SSMD) support, boardobj offset
will be part of SSMD lookup table which is part of PMU super surface
buffer & updated by PMU RTOS during init stage,
So, making changes to use common BOARDOBJGRP SET/GET_STATUS
construct define which fetchs offset/size from SSMD,
& deleting other BOARDOBJGRP construct defines.
JIRA NVGPU-1874
Change-Id: I4e3d9ad31da33a836c5e9219321c68d867c2a172
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2000860
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2019-02-07 04:15:31 -08:00
rmylavarapu
0f93cd23eb
gpu: nvgpu: Add support for new output type in VFE table
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Changes:
1. Added a new type: CTRL_PERF_VFE_EQU_OUTPUT_TYPE_THRESHOLD
This parameter was added in VFE table(under index 36) of 4F VBIOS to
convert VFE floating point output into threshold percentage value for
Fmon threshold programming.
Bug 2500899
Change-Id: Ife72e9a7b644c289702b0bcc89a1c9dce9d60386
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2011177
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2019-02-07 03:04:29 -08:00
Abdul Salam
0f2bbca0df
gpu: nvgpu: Remove extra perf load RPC
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1.Remove perf_pmu_load which calls the perf load RPC.
This is already done in pmu_vfe_load and needs only once.
2.Replace LOAD with VF_INVALIDATE.
MSG_ID_VFE_CALLBACK should call VF_INVALIDATE and not LOAD.
3.Move the clk arb WQ after VF_INVALIDATE for synchronization.
4.Move the perf load RPC after PMU setup.
Bug 200454682
Change-Id: I799588c102dd7328f0a43ed953f91a3a8b6b91e9
Signed-off-by: Abdul Salam <absalam@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2012338
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2019-02-06 15:23:49 -08:00
Nicolas Benech
9467646a87
gpu: nvgpu: nvgpu_cond_signal to return void
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes nvgpu_cond_signal and nvgpu_cond_signal_interruptible
to return void since no callers were using the return value.
JIRA NVGPU-677
Change-Id: I406309bde247e7ca656c91be1ea5ab742b0a045a
Signed-off-by: Nicolas Benech <nbenech@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2007563
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2019-01-31 12:04:10 -08:00
Antony Clince Alex
6a31f02a2d
gpu: nvgpu: Stop vfe state change thread during unload
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As part of vfe init a thread was created which is not getting
destroyed during de-init causing thread to access invalid memory
which is already freed.
Bug 2461665
Change-Id: I0770c7c6f293c1026a2c86715bdbe93f233e97c0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/1990089
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2019-01-25 01:35:33 -08:00
Terje Bergstrom
dce78f7332
gpu: nvgpu: Move PMU code to common/pmu
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Move code interfacing with PMU tasks to common/pmu.
JIRA NVGPU-961
Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/1950991
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2019-01-10 20:09:55 -08:00
