Philip Elcan
a789034209
gpu: nvgpu: pstate: update type for size param
...
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.
JIRA NVGPU-1008
Change-Id: I4e1aca8c061ec8ee6da7428f6bc200437894dc57
Signed-off-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2011438
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2019-02-11 14:04:39 -08:00
Mahantesh Kumbar
f7acf93345
gpu: nvgpu: Change in pstate s/w setup sequence
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pstate s/w setup needs to know offsets of boardobjs present
in PMU super surface to construct boardobj set/get_status
construct.
With SSMD support, boardobj offset will be part of SSMD
lookup table which is part of PMU super surface buffer &
updated by PMU RTOS during init stage.
As SSMD is updated at init stage & SSMD will be ready for nvgpu
to read offsets only when PMU init message is received,
so pstate s/w must wait till PMU is ready to construct
boardobj set/get_status
JIRA NVGPU-1874
Change-Id: I87d840965b92c538f26dbedf458f0c18d1808abc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/2000863
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2019-02-07 04:15:42 -08:00
Abdul Salam
0f2bbca0df
gpu: nvgpu: Remove extra perf load RPC
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1.Remove perf_pmu_load which calls the perf load RPC.
This is already done in pmu_vfe_load and needs only once.
2.Replace LOAD with VF_INVALIDATE.
MSG_ID_VFE_CALLBACK should call VF_INVALIDATE and not LOAD.
3.Move the clk arb WQ after VF_INVALIDATE for synchronization.
4.Move the perf load RPC after PMU setup.
Bug 200454682
Change-Id: I799588c102dd7328f0a43ed953f91a3a8b6b91e9
Signed-off-by: Abdul Salam <absalam@nvidia.com >
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2019-02-06 15:23:49 -08:00
Philip Elcan
725daf3400
gpu: nvgpu: pmu: fix MISRA 10.3 issues in pstate
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MISRA Rule 10.3 prohibits implicit assignment of an object of different
essential type or narrower type. This change addresses a number of
miscellaneous violations in pstate.c
JIRA NVGPU-1008
Change-Id: Iccde60d0110681f72f37dc64b2e67983757ad563
Signed-off-by: Philip Elcan <pelcan@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/1995882
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2019-01-18 13:54:45 -08:00
Terje Bergstrom
dce78f7332
gpu: nvgpu: Move PMU code to common/pmu
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Move code interfacing with PMU tasks to common/pmu.
JIRA NVGPU-961
Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com >
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2019-01-10 20:09:55 -08:00
