Commit Graph

31 Commits

Author SHA1 Message Date
Nicolas Benech
0ee3bad34a gpu: nvgpu: fix MISRA 17.7 in falcon_clear_intr
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes calls to nvgpu_falcon_clear_halt_intr_status to
handle error codes.

JIRA NVGPU-677

Change-Id: I079402e3056fd880a6cd260ef2aa62bb075c44bd
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008808
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-07 16:54:33 -08:00
Nicolas Benech
34b34915f8 gpu: nvgpu: fix MISRA 17.7 in falcon_bootstrap
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes calls to nvgpu_falcon_bootstrap to handle
error codes.

JIRA NVGPU-677

Change-Id: I1d9df6053c727e7eb3d99682ff7bb06267608a54
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008797
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-07 16:54:30 -08:00
Alex Waterman
5b5608f221 gpu: nvgpu: Delete unused source file mclk_gp106.c
Also delete the corresponding header file and all references to
said header file (mclk_gp106.h).

JIRA NVGPU-1737

Change-Id: I2376f03f7393784af72b20a789bf9cfda4871725
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995064
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-01-15 00:04:18 -08:00
Sagar Kamble
32280be158 gpu: nvgpu: update timed falcon state checks
falcon wait_idle, mem_scrub_wait, wait_for_halt, clear_halt_intr_status
routines have similar structure of returning -EINVAL on invalid falcon
parameter, invoking flcn_ops and returning -ETIMEDOUT on failure to
satisfy the condition. Fix the deviations.

JIRA NVGPU-1732

Change-Id: I95c907aacf02431604fa1502c688b376fa27ebbe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989988
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-14 21:44:14 -08:00
Sai Nikhil
889653b198 gpu: nvgpu: gp106: fix MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: Ie3d1a46c082d7589ea5d00c3d769086f046ae101
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829916
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2018-11-27 13:34:21 -08:00
Sagar Kamble
fd332ca6b4 gpu: nvgpu: s/*_flcn_*/*_falcon_*
There is mixed usage of falcon & flcn in function and data types.
Lets update all with "falcon" for consistency with file names.

JIRA NVGPU-1459

Change-Id: I02dbc866ce2cca009f2e8b87cfe11a919ec10749
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1953793
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-11-21 23:04:36 -08:00
Amurthyreddy
1023c6af14 gpu: nvgpu: MISRA 14.4 boolean fixes
MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.

Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.

JIRA NVGPU-1022

Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943058
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2018-11-07 10:35:22 -08:00
Amurthyreddy
f8ce19f879 gpu: nvgpu: MISRA 14.4 Function pointer as boolean
MISRA rule-14.4 doesn't allow the usage of function pointers & integer
types as booleans in the controlling expression of an if statement or
an iteration statement.

Fix violations where a function pointer or a function whose return
value is an integer, is used as a boolean in the controlling expression
of if and loop statements.

JIRA NVGPU-1021

Change-Id: Ic5336268394ba4396ce80744c25930d2fb44dc42
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932147
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-10-24 17:01:39 -07:00
Amurthyreddy
c94643155e gpu: nvgpu: MISRA 14.4 err/ret/status as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.

JIRA NVGPU-1019

Change-Id: I8c9ad786a741b78293d0ebc4e1c33d4d0fc8f9b4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921260
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-10-22 08:53:34 -07:00
Amurthyreddy
9b8185b261 nvgpu: gp106: MISRA 10.1 boolean fixes
Fix violations where a variable of type non-boolean is used as a
boolean in gpu/nvgpu/gp106.

JIRA NVGPU-646

Change-Id: I2c56f87b36c6144497a34438006933c34e381ccb
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1815523
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-10-12 17:35:09 +05:30
Terje Bergstrom
2c17e71aa1 gpu: nvgpu: Add MC APIs for reset masks
Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.

JIRA NVGPU-954

Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
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2018-10-12 17:35:07 +05:30
Debarshi Dutta
032860d8de gpu: nvgpu: move header location of gk20a.h
change the path of gk20a.h to <nvgpu/gk20a.h> for files in the
following directories.

gp106/
gv100/

Jira NVGPU-597

Change-Id: I098c12c34cdce764e6fca4ea1d16c5f8dee81026
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1836707
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-09-24 21:18:17 -07:00
Deepak Nibade
cec1d92300 gpu: nvgpu: print BIOS version during dGPU boot
Printing BIOS version during dGPU boot could be helpful for debugging

Change-Id: I910143f6e0008aa9fd6999d464af2d1930cfe8d5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832949
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-09-20 10:53:56 -07:00
Srirangan
e3710e5431 gpu: nvgpu: gp106: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I8493274995ed8de526902dd0ca0808b2972e28aa
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796806
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-08-29 08:59:35 -07:00
Srirangan
6b26d23349 gpu: nvgpu: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces
including single statement loop bodies. This patch fix the MISRA
violations due to single statement loop bodies without braces by adding
them.

JIRA NVGPU-989

Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791194
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-08-09 22:28:15 -07:00
Debarshi Dutta
82a90170d3 gk20a: nvgpu: Remove io.h dependency from gk20a.h
In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h

JIRA NVGPU-597

Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
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2018-07-30 11:24:06 -07:00
Deepak Nibade
5f8bb126a0 gpu: nvgpu: add NULL check for enable/disable_shadow_rom HALs
gops.xve.enable_shadow_rom and gops.xve.disable_shadow_rom HALs could be NULL
on some platforms
Execute them only if they are defined

Jira NVGPUT-120

Change-Id: I683d74a850372f442291a419951a2376805eb1e5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772559
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-07-06 13:26:32 -07:00
Deepak Nibade
97d697a848 gpu: nvgpu: increase bios size to 0x90000
bios size is currently set to 0x40000, but this could insufficient on
some platforms

Increase it to 0x90000 so that we have buffer of sufficient size to
store bios content

Change-Id: I510d10763b1fc6ba427680e44a55e3604f67e049
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1746578
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-06-14 06:44:08 -07:00
Deepak Nibade
6266a1210d gpu: nvgpu: add HALs for devinit and preos bios operations
Add below new HALs for bios operations
gops.bios.devinit()
gops.bios.preos()
gops.bios.verify_devinit()

Export existing APIs gp106_bios_devinit() and gp106_bios_preos() and set them
to above HALs on gp106 and gv100

And call new HALs from gp106_bios_init() if supported instead of directly
calling APIs

Jira NVGPUT-48

Change-Id: Ic89f1c86cf6e3e0785b3663fe733b201d6f2f773
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1708382
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2018-05-18 09:28:36 -07:00
Terje Bergstrom
dd739fcb03 gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.

Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.

Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
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2018-05-09 18:26:04 -07:00
Terje Bergstrom
a51219e526 gpu: nvgpu: Store VBIOS version in g->bios
Store VBIOS version in g->bios instead of GPU characteristics. This
removes a few Linux dependencies from common code, because GPU
characteristics is defined in Linux IOCTL header.

JIRA NVGPU-259

Change-Id: I9aab3d37b7ca000edd59c92b8601a96ee288e2bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593684
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2017-11-07 22:19:05 -08:00
Terje Bergstrom
a5e76ed7af gpu: nvgpu: Remove pg419 emulation on pg418
Remove emulation of pg419 board with a pg418 which does not have
a power sensor, but claims to have one in VBIOS.

JIRA NVGPU-259

Change-Id: I6527d08dd05b79f96e505561685504bb239ab4ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588732
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-11-01 15:26:37 -07:00
Alex Waterman
3fdb6d2e31 gpu: nvgpu: Remove Linux headers from mm_gk20a.h
Delte the Linux headers and make some modifications to get rid of the
minor compilation issues that resulted.

  - Add <linux/iommu.h> to os_linux.h
  - Delete #if 0 code that "flushed" a buffer in gr_gk20a.c
  - Delete FLUSH_CPU_DCACHE() macro
  - Move the cache flush definitions to <nvgpu/linux/vm.h>
    and include this header in sim_gk20a.c. This file will
    not be used by QNX so this should be fine.
  - Add <linux/pci_ids.h> to gp106/bios_gp106.c and
    gp106/mclk_gp106.c.
  - Move function to common/linux/dmabuf.h since it is a
    dmabuf related function and uses a struct device pointer
    as an argument.

JIRA NVGPU-30

Change-Id: I11f56b98524c7fac3efa91b4686592130e5f8a46
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585510
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2017-10-27 14:45:58 -07:00
Terje Bergstrom
30b9cbe35a gpu: nvgpu: Remove bios_blob debugfs
linux/debugfs.h was included in gk20a.h because of the debugfs entry
bios_blob, which can be used for checking contents of VBIOS. That
has never been used, so instead of abstracting it, this patch removes
the feature altogether.

Two files were using debugfs but did not #include <linux/debugfs.h>.
They failed to build now that gk20a.h no longer #includes it, so
added explit #include.

JIRA NVGPU-259

Change-Id: Ie1ea9be1a8920441b1616f34e64e505e6e10e38c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570404
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2017-10-16 13:34:56 -07:00
David Nieto
7c5cf70268 gpu: nvgpu: add support for pre-os FW
Pre-os firmware takes care, among others, of the control of FAN till
the driver takes over its control. On some GPUs not enabling this FW can lead
tp physical board damage, hence it is needed to run this firmware.

JIRA: NVGPUGV100-9

Change-Id: I18d54cfd5eb64ecec79c5dae67ac8d5bb1facf36
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549035
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-10-10 12:05:42 -07:00
Terje Bergstrom
7885500a42 gpu: nvgpu: Change license for common files to MIT
Change license of OS independent source code files to MIT.

JIRA NVGPU-218

Change-Id: I1474065f4b552112786974a16cdf076c5179540e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565880
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2017-09-26 11:37:32 -07:00
David Nieto
90568a2ce5 gpu: nvgpu: allow bind to be interrupted
This change solves two problems:

(*) the possibility of a crash due to interrupting the gpu
initialization following a bind
(*) a IOVA memory leak that could prevent the GPU from binding after
about 200 bind/unbind cycles

A detailed list of fixes:

- chek that arbiter is initialized before freeing it.
- do not re-enable interrupts when MSI is enabled on unbind.
- free the semaphore sea on unbind.
- ensure we dont double load the vbios.
- check return value of nvgpu_mutex_init for semaphores.
- add corresponding nvgpu_mutex_destroy calls.

bug 1816516

Change-Id: Ia8af73019e0e1183998855d55bb3eea09672a8b7
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1465302
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: David Jarrett <djarrett@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563019
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2017-09-22 15:47:01 -07:00
Terje Bergstrom
774899f30a gpu: nvgpu: Change VBIOS code to use gp106 headers
VBIOS code was the last code using gm206 hardware headers. Change the
code to use gp106 headers instead, move the code to gp106 directory
and delete gm206 HW headers.

JIRA NVGPU-218

Change-Id: I7ccd6c2975c767bca871d77a701dbd3395b17f30
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563742
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-09-20 15:55:32 -07:00
Terje Bergstrom
53465def64 gpu: nvgpu: Generalize BIOS code
Most of BIOS parsing code is not specific to any particular GPU. Move
most of the code to generic files, and leave only chip specific parts
dealing with microcontroller boot into chip specific files.

As most of the parsing is generic, they do not need to be called via
HALs so remove the HALs and change the calls into direct function
calls.

All definitions meant to be used outside BIOS code itself are now in
<nvgpu/bios.h>

Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302222
GVS: Gerrit_Virtual_Submit
2017-02-17 13:46:32 -08:00
Alex Waterman
78ad8a23ea gpu: nvgpu: Move gp106 HW headers
Move the gp106 HW headers to a new directory specially for them:

  include/nvgpu/hw/gp106

And change the code to include like so:

  #include <nvgpu/hw/gp106/hw_fb_gp106.h>

This is part of the process to restructure the nvgpu driver.

Bug 1799159

Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1280327
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-11 12:44:15 -08:00
David Nieto
905f1c0392 gpu: nvgpu: parse and execute mclk shadow script
* Parsing of shadow registers from VBIOS
 * Partial devinit engine interpreter implementation

JIRA DNVGPU-117

Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1214956
Reviewed-on: http://git-master/r/1237293
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:26:50 +05:30